Low-cost Field Programmable Gate Array Research Articles

Design methodology for fully dynamic-controlled polynomial profiles and reduced tracking error in CNC machines

High speed and high precision on computer numerically controlled (CNC) machines are major issues for most industrial automation processes. Among the most important factors for precise motion control are the control law, the controller implementation, and the profile reference. The effects of the control law and controller implementation on the tracking error in CNC machines have been widely studied, while the issue of profile reference has not received the required attention. To improve the dynamics provided by the conventional profile reference, several techniques have been proposed, focusing on peak jerk limitation. The novelty of this work is to develop a generalized methodology designed for producing dynamically constrained higher degree piecewise polynomial profiles, without limits in maximum polynomial degrees. They lead to define in an arbitrary way the dynamics shape, while the peak dynamics values constrained are maintained in order to improve the tracking error on CNC systems and giving the possibility to design fully dynamic-controlled trajectories. For experimentation purposes, a two-axis proportional–integral–derivative controller and profile reference generator are implemented in a low-cost field programmable gate array. The experimentation demonstrates the efficiency of the proposed methodology, showing the peak jerk and tracking error reduction, compared against recent reports from literature.

Development of a Low-Cost FPGA-Based SSVEP BCI Multimedia Control System

This paper proposes a low-cost field-programmable gate-array (FPGA)-based brain-computer interface (BCI) multimedia control system, different from the BCI system, which uses bulky and expensive electroencephalography (EEG) measurement equipment, personal computer, and commercial real-time signal-processing software. The proposed system combines a customized stimulation panel, a brainwave-acquisition circuit, and an FPGA-based real-time signal processor and allows users to use their brainwave to communicate with or control multimedia devices by themselves. This study also designs a light-emitting diode stimulation panel instead of cathode ray tube or liquid-crystal display used in existing studies, to induce a stronger steady-state visual evoked potential (SSVEP), a kind of EEG, used as the input signal of the proposed BCI system. Implementing a prototype of the SSVEP-based BCI multimedia control system verifies the effectiveness of the proposed system. Experimental results show that the subjects' SSVEP can successfully control the multimedia device through the proposed BCI system with high identification accuracy.

Automatic volumetric gas flow meter for monitoring biogas production from laboratory-scale anaerobic digester

Biogas rate production is a relevant variable in anaerobic digestion processing, where, an indicator of volatile solids conversion rate or an earlier indicator of digester failure is needed. Reconfigurable devices like Field Programmable Gate Arrays (FPGAs) have advantages over microprocessors and DSPs with similar logic complexity because their open architecture makes them suitable for system on-a-chip applications. The contribution of this work is the development of an improved water displacement gas flow meter, intended to be used in laboratory-scale anaerobic digestion reactors. Results show automatic gas flow meter functionality, where its calibration stability promotes reliable biogas rate production readings. The synthesis of its digital processing and control system into a low-cost FPGA platform had permitted the successful application of the digital data acquisition and processing in a standalone water displacement gas flow meter.

Designing AES cryptographic unit for automatic implementation in low-cost FPGA devices

This paper presents original research results that show viable options for implementation of the advanced encryption standard (AES) cipher (both encoding and decoding paths) in low cost field programmable gate arrays (FPGA). The discussion begins with those aspects of the four basic cipher transformations that are essential for realisation with resources available in FPGA devices, then moves to various possible organisations of the cipher unit and concludes with efficiency and size comparison of results obtained after implementation of the AES-128 version of the method in Spartan-3 devices from Xilinx. The compared design options were implemented with a standard and widely used ISE software with XST synthesis tool. No hand optimisation or fine-tuning of the implementation steps were performed: the synthesis, mapping, placement and routing were all done fully automatically by the software. While this approach will always be inferior to the top-performance hand-optimised designs known in the literature, its automatic implementation brings specific advantages in projects where the unit must co-exist with other parts of the system and elaborated optimisations are either limited or undesired.

FPGA-Based Multiple-Channel Vibration Analyzer for Industrial Applications in Induction Motor Failure Detection

Early detection of failures in equipment is one of the most important concerns to industry. Many techniques have been developed for early failure detection in induction motors. There is the necessity of low-cost instrumentation for online multichannel measurement and analysis of vibration in the frequency domain, and this could be fixed to the machine for continuous monitoring to provide a reliable continuous diagnosis without needing trained staff. Field-programmable gate arrays (FPGAs) are distinguished by being very fast and highly reconfigurable devices, allowing the development of scalable parallel architectures for multichannel analysis without changing the internal hardware. The novelty of this work is the development of a low-cost FPGA based on a multichannel vibration analyzer; this is capable of providing an automatic diagnosis of the motor state carrying out online continuous monitoring. To test the functionality of the proposed vibration analyzer, three experiments on 746-W (1-hp) induction motors were carried out. Such experiments are intended to detect motor failures such as broken bars, unbalance, and looseness. The obtained results show the overall system performance.

Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router

The sequential greedy scheduling (SGS) algorithm is a scalable maximal matching algorithm. This algorithm was conceptually proposed and well received since it provides non-blocking in an Internet router with input buffers and a cross-bar, unlike other existing implementations. In this paper, we implement a new design of the SGS algorithm, and determine its exact behaviour, performance and QoS that it provides. We examine different design options and measure the performance of their implementations in terms of their scalability and speed. It will be shown that multiple scheduler modules of a terabit Internet router can be implemented on a low-cost field-programmable gate-array (FPGA) device, and that the processing can be performed within the desired time slot duration. Proper functioning of the implemented scheduler was confirmed through thorough software and hardware testing.

Real-Time Hand-Held Ultrasound Medical-Imaging Device Based on a New Digital Quadrature Demodulation Processor

A fully hardware-based real-time digital wideband quadrature demodulation processor based on the Hilbert transform is proposed to process ultrasound radio frequency signals. The presented architecture combines 2 finite impulse response (FIR) filters to process in-phase and quadrature signals and includes a piecewise linear approximation architecture that performs the required square root operations. The proposed implementation enables flexibility to support different transducers with its ability to load on-the-fly different FIR filter coefficient sets. The complexity and accuracy of the demodulator processor are analyzed with simulated RF data; a normalized residual sum-of-squares cost function is used for comparison with the Matlab Hilbert function. Three implementations are integrated into a hand-held ultrasound system for experimental accuracy and performance evaluation. Real-time images were acquired from a reference phantom, demonstrating the feasibility of using the presented architecture to perform real-time digital quadrature demodulation of ultrasonic signal echoes. Experimental results show that the implementation, using only 2942 slices and 3 dedicated digital multipliers of a low-cost and low-power field-programmable gate array (FPGA) is accurate relative to a comparable software- based system; axial and lateral resolution of 1 mm and 2 mm, respectively, were obtained with a 12-mm piezoelectric transducer without postprocessing. Because the processing and sampling rates are the same, high-frequency ultrasound signals can be processed as well. For a 15-frame-per-second display, the hand-held ultrasonic imaging-processing core (FPGA, memory) requires only 45 mW (dynamic) when using a 5-MHz single-element piezoelectric transducer.

Novel Methodology for Online Half-Broken-Bar Detection on Induction Motors

The relevance of the development of monitoring systems for rotating machines is not only the ability to detect failures but is also how early these failures can be detected. Squirrel-cage induction motors are the most popular motors used in industry, consuming around 85% of the power in industrial plants. Broken rotor bars in induction motors are among the major failures that are desirable to detect at early stages because this failure significantly increases power consumption and is responsible for further damage to the machinery. Previously reported works base their analysis on current or vibration monitoring for broken-bar detection up to one broken bar under mechanically loaded motor conditions. The contribution of this paper presents a novel methodology for half-broken-bar detection, which combines current and vibration analysis by correlating the signal spectra to enhance detectability for mechanically loaded and unloaded operating conditions of the motor, which the other isolated techniques are unable to detect. The proposed methodology is implemented in a low-cost field-programmable gate array (FPGA), giving a special-purpose system-on-a-chip (SoC) solution for online operation, with the development of a complex postprocessing decision-making unit. Several cases of study are presented to demonstrate the performance of the implementation.

FPGA Implementation of a Digital Sequential Phase-Shift Stroboscope for In-Plane Vibration Measurements With Subpixel Accuracy

This paper describes a sequential phase-shift stroboscope and a subpixel imaging system that is able to measure with high resolution weak in-plane harmonic motions, such as those of microelectromechanical systems (MEMS). The synchronization of both MEMS stimulus and light strobe can be obtained by either using the camera output frame signal or driving the external trigger of the camera, depending on the operation principle of the camera. Experimental results concern a small silicon cantilever resonator excited in its first and second vibration modes and a quartz tuning fork. Two optical configurations have been developed. The first one is based on the use of a macroobjective for large fields of view with micrometer resolution displacement measurement, and the second is based on an optical microscope for weak amplitude vibration measurements with a resolution down to a few nanometers. The whole logic unit of the stroboscopic signal generator is implemented into a low-cost field-programmable gate array, thus offering high flexibility.

Multilevel Multiphase Space Vector PWM Algorithm

In the last few years, interest in multiphase converter technology has increased due to the benefits of using more than three phases in drive applications. Besides, multilevel converter technology permits the achievement of high power ratings with voltage limited devices. Multilevel multiphase technology combines the benefits of both technologies, but new modulation techniques must be developed in order to take advantage of multilevel multiphase converters. In this paper, a novel space vector pulsewidth modulation (SVPWM) algorithm for multilevel multiphase voltage source converters is presented. This algorithm is the result of the two main contributions of this paper: the demonstration that a multilevel multiphase modulator can be realized from a two-level multiphase modulator, and the development of a new two-level multiphase SVPWM algorithm. The multiphase SVPWM algorithm presented in this paper can be applied to most multilevel topologies; it has low computational complexity and it is suitable for hardware implementations. Finally, the algorithm was implemented in a low-cost field-programmable gate array and it was tested in a laboratory with a real prototype using a five-level five-phase inverter.

Automatic Online Diagnosis Algorithm for Broken-Bar Detection on Induction Motors Based on Discrete Wavelet Transform for FPGA Implementation

Overall system performance on a production line is one of the major concerns in modern industry where induction motors are present and their condition monitoring is mandatory. Periodic offline monitoring of the motor condition is usually performed in the industry, consuming production time and increasing cost. Broken rotor bars are among the most common failures in induction motors. Reported research projects give a broken-rotor-bar-detection methodology based on personal-computer implementation that is performed offline and requires an expert technician interpretation which is not a cost-effective solution. The novelty of this paper is the development of an automatic online diagnosis algorithm for broken-rotor-bar detection, optimized for single low-cost field-programmable gate-array (FPGA) implementation, which guarantees the development of economical self-operated equipment. The proposed algorithm requires less computation load than the previously reported algorithms, and it is mainly based on the discrete-wavelet-transform application to the start-up current transient; a further single mean-square computation determines a weighting function that, according to its value, clearly points the motor condition as either healthy or damaged. In order to validate the proposed algorithm, several tests were performed, and an FPGA implementation was developed to show the algorithm feasibility for automatic online diagnosis.

The application of reconfigurable logic to high speed CNC milling machines controllers

Reconfigurable logic has gained relevance in high-speed computer numerical control (CNC) digital controllers where high processing speed at the servo loop update time is critical. Reconfigurable devices like field programmable gate array (FPGA) have advantages over microprocessors and DSP with similar logic complexity because their open architecture makes them suitable for system on-a-chip applications. The contribution of this work is the development of an FPGA-based proportional–integral–derivative (PID) controller applied to a high-speed CNC milling machines in order to achieve the servo loop update time requirements. Results show PID system functionality, which has been synthesized into a low-cost FPGA platform, successfully applied to a high-speed CNC milling machine.

A hardware implementation of artificial neural networks using field programmable gate arrays

An artificial neural network algorithm is implemented using a low-cost field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time. In this work, the training of the network is performed in the off-line computing environment and the results of the training are configured to the hardware in order to minimize the latency of the neural computation. With five 8-bit input patterns, six hidden nodes, and one 8-bit output, the implemented hardware neural network makes decisions on a set of input patterns in 11 clock cycles, or less than 200 ns with a 60 MHz clock. The result from the hardware neural computation is well predictable based on the off-line computation. This implementation may be used in level 1 hardware triggers in high energy physics experiments.

A 90-nm Low-Power FPGA for Battery-Powered Applications

Programmable logic devices such as field-programmable gate arrays (FPGAs) are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than application-specified integrated circuits and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications. Our design is based on a commercial low-cost FPGA and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90-nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode and wakes up from standby mode in approximately 100 ns

A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers

Two-dimensional (2-D) convolution is widely used in image and video processing. Although the operation is simple, 2-D convolution is however both computationally expensive and memory-intensive. Field-programmable-gate-array (FPGA)-based parallel processing architectures were proposed to accelerate calculations for 2-D convolution. And data buffers implemented with FPGA on-chip resources were used to avoid direct access to external memories. Full buffering and partial buffering (PB) schemes were adopted in previous works. The former would consume a large amount of FPGA resources, while the latter would cause a sharp increase in external memory bus bandwidth. In this brief, we present a multiwindow PB scheme for FPGA-based 2-D convolvers. Compared with the aforementioned methods, the new buffering strategy exhibits a good balance between on-chip resource utilization and external memory bus bandwidth, and therefore is suitable for low-cost FPGA implementation

The progressive focusing correction technique for ultrasound beamforming

This work presents a novel method for digital ultrasound beamforming based on programmable table look-ups, in which vectors containing coded focusing information are efficiently stored, achieving an information density of a fraction of bit per acquired sample. Timing errors at the foci are within half the period of a master clock of arbitrarily high frequency to improve imaging quality with low resource requirements. The technique is applicable with conventional as well as with deltasigma converters. The bit-width of the focusing code and the number of samples per focus can be defined to improve both memory size and F# with controlled timing errors. In the static mode, the number of samples per focus is fixed, and in the dynamic approach that figure grows progressively, taking advantage of the increasing depth of focus. Furthermore, the latter has the lowest memory requirements. The technique is well suited for research purposes as well as for real-world applications, offering a degree of freedom not available with other approaches. It allows, for example, modifying the sampling instants to phase aberration correction, beamforming in layered structures, etc. The described modular and scalable prototype has been built using low-cost field programmable gate arrays (FPGAs). Experimental measurements are in good agreement with the theoretically expected errors.

Implementation of access controller for ethernet passive optical network

This paper presents the design and implementation of access controller used for Ethernet passive optical network (EPON). As a first step to develop an ASIC product, the entire system is designed on a field programmable gate array (FPGA) with an embedded CPU. To reduce working frequency of the FPGA, the byte-to-word conversion is proposed. Propagation delays are equalized by ranging procedure so as to avoid data collision. Implementations of synchronization, classification, as well as Linux porting are illustrated in detail. The interface between the FPGA and CPU are also presented. Experimental results show that the proposed system can properly function in a relatively low cost FPGA.

Theory and Implementation of a Computationally Efficient Decimation Filter for Power-Aware Embedded Systems

As analog-to-digital converters become faster, this will allow them to become closer to their intended sensor. This will foster an environment that will continue to allow a paradigm shift in which digital systems replace analog ones, thus mitigating many nonideal effects, lowering costs, and providing more compact computational platforms. In parallel with this trend, the importance of decimation filters will continue to expand, as the high-speed data will need to be downsampled prior to ingestion by a decision-making element, such as a digital signal processor running constant false alarm rate (CFAR) algorithms, neural networks, and the like. Ideally, these decimation filters should have as much stopband attenuation as possible and should not be hindered by timing bottlenecks. However, on a fixed-point processor, like a field-programmable gate array (FPGA), finite word-length effects are in opposition to this goal. To break this nexus, this paper employs a revolutionary integerization technique based on multidimensional continued fractions strategically coupled with an efficient multiplierless architecture design strategy. Multidimensional continued fractions have been known within the mathematical community for some time, which include the popular Furtwangler algorithm and the ordered Jacobi-Perron algorithm, but have been left unexplored in the engineering community until recently. Simultaneous rational representations (SRRs) are another member of the multidimensional continued fraction family and are employed here to create fixed integer transforms with computationally optimal representations. In addition, this paper also focuses on hardware implementations in low-cost FPGAs or application-specific integrated circuits, which benefit from multiplierless implementation to save hardware real estate. From a computational perspective, carefully choosing how to represent the coefficients of a transform may have dramatic effects on how many operations are consumed to implement it. In a low-order example, the number seven may be expressed as 23-20 or 22 +21+20. This concept coupled with SRRs is explored in this paper to yield low-power high-speed implementations for embedded systems

High-speed JPEG coder implementation for a smart camera

The compression standard of the Joint Photographic Experts Group (JPEG) for still images is used in many imaging applications. Although machine vision algorithms are based on raw images, massive data reduction of images in many applications is required additionally, e.g. to archive images in the context of automated visual inspection or to store high-speed image sequences when memory space is limited. Especially in embedded systems the software implementation of compression algorithms is too slow to meet real-time requirements. In this paper we present a fast implementation of a JPEG coder in a field programmable gate array (FPGA). This JPEG coder uses the architecture-specific function blocks of a low-cost FPGA (dedicated multipliers, block RAM). Nevertheless, there is hardly any limitation to the generality of the approach, as these building blocks are manufacturer-independent elements of up-to-date FPGA architectures.

Design of Low-Cost FPGA Hardware for Real-time ICA-Based Blind Source Separation Algorithm

Blind source separation (BSS) of independent sources from their convolutive mixtures is a problem in many real-world multi-sensor applications. In this paper, we propose and implement an efficient FPGA hardware architecture for the realization of a real-time BSS. The architecture can be implemented using a low-cost FPGA (field programmable gate array). The architecture offers a good balance between hardware requirement (gate count and minimal clock speed) and separation performance. The FPGA design implements the modified Torkkola's BSS algorithm for audio signals based on ICA (independent component analysis) technique. Here, the separation is performed by implementing noncausal filters, instead of the typical causal filters, within the feedback network. This reduces the required length of the unmixing filters as well as provides better separation and faster convergence. Description of the hardware as well as discussion of some issues regarding the practical hardware realization are presented. Results of various FPGA simulations as well as real-time testing of the final hardware design in real environment are given.