Low Complexity Hardware Implementation Research Articles

A Novel Method for Scalable VLSI Implementation of Hyperbolic Tangent Function

Hyperbolic tangent and Sigmoid functions are used as non-linear activation units in the artificial and deep neural networks. Since, these networks are computationally expensive, customized accelerators are designed for achieving the required performance at lower cost and power. The activation function and MAC units are the key building blocks of these neural networks. A low complexity and accurate hardware implementation of the activation function is required to meet the performance and area targets of such neural network accelerators. Moreover, a scalable implementation is required as the recent studies show that the DNNs may use different precision in different layers. This paper presents a novel method based on trigonometric expansion properties of the hyperbolic function for hardware implementation which can be easily tuned for different accuracy and precision requirements.

Joint Identification, Detection and Channel Estimation in Industrial IoT

Rapid identification and analysis of faulty or degraded sensors and devices are key challenge in Industrial Internet of Things (IIoT). Wireless communication is emerging as a viable solution to support the massive sensors and devices with sporadic fault due to low construction cost, low latency and high reliability. For future massive machine-type communications, Media-Based Modulation (MBM) is regarded as a promising technique to achieve high data rate with low-complexity hardware implementation. In this paper, only the sensors or devices with fault are activated to transmit data which use MBM to carry more fault information. A compressive sensing (CS)-based joint adaptively fault machine identification, data detection and channel estimation algorithm is proposed by taking full consideration of the prior information such as sparsity structure and physical variables correlation. The simulation results demonstrate that the proposed algorithm is superior to the state-of-the-art identification and detection methods.

A High-Accuracy Stochastic FIR Filter with Adaptive Scaling Algorithm and Antithetic Variables Method

Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.

Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography

Post-quantum cryptography (PQC) refers to the cryptosystem that can resist the attacks launched from mature quantum computers in the not far future and has recently gained intensive attention from the research community as most of the existing public-key cryptosystems are vulnerable to attacks from quantum computers. Ring-Learning-with-Errors (Ring-LWE)-based scheme is an essential type of the lattice-based PQC due to its strong security proof and ease of implementation. As the latest variant of the Ring-LWE, the binary Ring-LWE (BRLWE)-based scheme possesses even smaller computational complexity and thus is more suitable for resource-constrained applications. However, the existing works have not well covered various aspects related to this new scheme, especially on the low-complexity hardware implementation. In this paper, we aim to present a novel implementation of the BRLWE-based scheme on the hardware platform with very low-complexity with this point of view. To carry out the specified work in a successful manner, we have proposed mainly four layers of coherent interdependent efforts: (i) we have provided the necessary algorithmic derivation process in detail to formulate the desired algorithm for the polynomial multiplication over hybrid fields, which is the major arithmetic component of the BRLWE scheme; (ii) we have presented the corresponding hardware architecture in a thorough format with sufficient description of the internal structures; (iii) we have also provided the complexity analysis and implementation-based comparison to demonstrate the superior performance of the proposed polynomial multiplication over the state-of-the-art design; (iv) finally, we have extended the proposed low-complexity polynomial multiplication to the major operational phase of the BRLWE scheme. We have shown that the proposed BRLWE structure involves significantly lower area-time complexities over the existing design, e.g., the proposed design has at least 66.01% less area-delay product (ADP) than the newly reported (Straix V device). Overall, the proposed design and implementation strategies are highly efficient, and the proposed BRLWE structure is desirable for many emerging applications.

Lifting method for quasi-cyclic low-density parity-check codes based on approximated cycle extrinsic message degree in optical communication systems

Quasi-cyclic low-density parity-check (QC-LDPC) codes with low-complexity hardware implementation and excellent performance have become a hot research topic in many optical communication systems. To meet the different requirements of code lengths in optical communication systems, lifting methods which remove all the short cycles equally are usually used to construct long QC-LDPC codes of larger lengths by lifting short QC-LDPC codes. A lifting method is proposed, which considers both length and connectivity of short cycles. The proposed lifting method reduces the complexity of calculating the approximated cycle extrinsic message degree -related metrics and improves connectivity of the Tanner graph. The numerical results prove that, by employing our proposed lifting method, the lifted long QC-LDPC codes have better bit error rate performance compared with the lifted codes employing the traditional lifting method.

String Prediction for 4:2:0 Format Screen Content Coding and Its Implementation in AVS3

In the past, string prediction (also known as string matching) was applied only to RGB and YUV 4:4:4 format screen content coding. This paper proposes a string prediction approach to 4:2:0 format screen content coding implemented in the third generation of Audio Video Standard (AVS3) in China. String prediction is applied to both YUV CU and Y CU. To further improve the coding performance, several improved technicals of string prediction are presented, including a mixed string searching strategy for finding the optimal reference string, a joint picture-level, CU-level, and pixel-level early termination strategy to reduce coding complexity, and two effective coding methods for string prediction parameters. For low-complexity hardware implementation of string prediction decoder, the memory access bandwidth is reduced by introducing string constraints. Meanwhile, string prediction reuses the reference pixel buffer of intra block copy (IBC). Compared with the newest AVS3 reference software HPM7.0 with string prediction disabled, the proposed string prediction approach achieves up to 18.48% Y BD-rate reduction. Using AVS3 Screen Content Coding (SCC) Common Test Condition and YUV test sequences in Text and Graphics with Motion category, the proposed technique achieves an average Y BD-rate reduction of 10.33%, 8.47%, 6.91% for All Intra (AI), Random Access (RA) and Low Delay (LD) configurations, respectively, with low additional encoding and decoding complexity. The proposed string prediction approach has been adopted in the newest AVS3 reference software HPM7.0.

Binary CorNET: Accelerator for HR Estimation From Wrist-PPG.

Research on heart rate (HR) estimation using wrist-worn photoplethysmography (PPG) sensors have progressed rapidly owing to the prominence of commercial sensing modules, used widely for lifestyle monitoring. Reported methodologies have been fairly successful in mitigating the effect of motion artifacts (MA) in ambulatory environment for HR estimation. Recently, a learning framework, CorNET, employing two-layer convolution neural networks (CNN) and two-layer long short-term network (LSTM) was successfully reported for estimating HR from MA-induced PPG signals. However, such a network topology with large number of parameters presents a challenge, towards low-complexity hardware implementation aimed at on-node processing. In this paper, we demonstrate a fully binarized network (bCorNET) topology and its corresponding algorithm-to-architecture mapping and energy-efficient implementation for HR estimation. The proposed framework achieves a MAE of 6.67 ± 5.49bpm when evaluated on 22 IEEE SPC subjects. The design, synthesized with ST65 nm technology library achieving 3 GOPS @ 1 MHz, consumes 56.1 μJ per window with occupied 1634K NAND2 equivalent cell area and had a latency of 32 ms when estimating HR every 2s from PPG signals.

P-SFA: Probability based Sigmoid Function Approximation for Low-complexity Hardware Implementation

A probability-based sigmoid function approximation (P-SFA), which is based on piecewise linear function and neuron's values statistical probability distribution in each layer, is proposed to lower the complexity of neural network hardware implementation with only addition circuit. The sigmoid function is divided into three fixed regions, and the number of sub-regions with different sizes in each fixed region is adapted to neuron's values distribution in each layer to reduce the error between the sigmoid function and P-SFA function. The experimental results on FPGA show that the P-SFA function is efficient in terms of power and speed, and the recognition accuracies in DNN and CNN for MNIST with P-SFA are the highest among the state-of-the-art methods, up to 97.46% and 99.02% respectively.

Digital Predistortion of 5G Massive MIMO Wireless Transmitters Based on Indirect Identification of Power Amplifier Behavior With OTA Tests

In this article, we present a novel digital predistortion (DPD) architecture for multiple-input–multiple-output (MIMO) transmitters using a real-time single-channel over-the-air (OTA) data acquisition loop. The proposed feedback data acquisition strategy captures OTA signals from a fixed location and indirectly identifies the nonlinear behavior of all power amplifiers (PAs) in the array, as well as their combined signals in the far-field direction. The DPD can, therefore, be effectively constructed without direct measurement at PA output or at user end. The proposed linearization solution can run in real-time and, thus, does not interfere with data transmission in the MIMO transmitters. It can also achieve robust performance when mutual coupling occurs between antenna elements. Simulation and experimental results demonstrate that the proposed scheme can accurately estimate both PA outputs and far-field main beam data. Excellent linearization performance can be achieved with low complexity hardware implementation and reduced computational complexity.

Design and Evaluation of an Acoustic Modem for a Small Autonomous Unmanned Vehicle

Design of underwater acoustic (UWA) modems for compact-sized, underwater platforms such as autonomous underwater vehicles (AUVs) is challenging because of the practical requirement to keep an engineering balance between the performance and the system overhead. Considering this type of mobile communication scenario, Doppler spread as well as the multipath draws substantial attention in implementing the system’s design and engineering. Specifically, for a small AUV, the large computational complexity of real-time resampling for the classic Doppler correction poses significant difficulty for the limited capability of the low-cost processor. In this paper, by adopting an adjustable AD (analog-to-digital) sampling rate, a Doppler compensation approach is proposed to enable low-complexity hardware implementation. Based on this, a direct sequence spread spectrum (DSSS) acoustic modem is designed for a low-cost, small-sized AUV. Meanwhile, the performance evaluation of this acoustic modem is conducted in terms of the robustness upon varying Doppler as well as AUV integration. Finally, experimental results performed on a commercial, small-sized AUV under different speeds are reported to verify the effectiveness of the proposed acoustic modem.

Efficient complex matrix inversion for MIMO OFDM systems

The use of orthogonal frequency-division multiplexing (OFDM) greatly simplifies receiver design in multiple-input multiple-output (MIMO) wireless systems when the channel is frequency selective. Since complex-valued matrix manipulations, such as matrix inversion, are normally required in MIMO-OFDM systems, the receiver complexity is much higher than that of single-input single-output and single-carrier systems. In this paper, the authors propose a low-complexity version of matrix inversion by using the dichotomous coordinate descent (DCD) algorithm for MIMO-OFDM systems. The idea is for the DCD algorithm to separately obtain the individual columns of the inverse of the matrix. Owing to the low-complexity hardware implementation of the individual DCD algorithm, a block of DCD processors can be adopted to obtain the columns of the inverse of the channel correlation matrix in parallel with low hardware occupation.

A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras

In this paper a 4928 × 3264 pixel CMOS image signal processor (ISP) is proposed for digital still cameras with low complexity and high performance. To reduce hardware cost and keep high performance, novel algorithms are proposed to process image signals. Firstly, a joint demosaic and denoise algorithm is presented for both color interpolation and Gaussian noise removal. This novel joint algorithm achieves high performance and saves line buffers. Furthermore, image edge enhancement is performed jointly with this algorithm to save memory cost. Secondly, a low complexity auto white balance hardware architecture is presented based on histogram equalization algorithm. This algorithm can handle some extremely bad scenes. To reduce hardware cost, the contrast enhancement is realized jointly with auto white balance. Thirdly, to remove pulse noise, a high performance and low complexity hardware implementation is proposed based on median filter using only nine comparators. Based on these algorithms and hardware, the VLSI architecture of the ISP is proposed and implemented in a SMIC 65nm CMOS technology. The gate count of the ISP is 158k and core area is 1.5mm2. Only 8 line buffers with total 462 Kb SRAM are used in the ISP. The throughput of the ISP is 12Gb/s with a frequency of 333MHz and power consumption of 77mW.

A Low-Complexity Hardware Implementation of Compressed Sensing-Based Channel Estimation for ISDB-T System

Compressed sensing (CS) is one of the hottest research topics in the sparse signal reconstruction problem. But CS implementation has a drawback of high computational complexity due to calculation between large size of matrices. In this paper, we will propose a low-complexity CS hardware realization for channel estimation in the integrated services digital broadcasting-terrestrial (ISDB-T) system using several optimization methods to reduce the implementation complexity of CS usage. Since the ISDB-T is based on orthogonal frequency division and multiplexing system, the measurement matrix of CS computation is a truncated discrete Fourier transform (DFT) matrix. We can exploit the symmetrical property of this DFT matrix to significantly reduce its multiplication complexity and random access memory usage. To achieve fast reconstruction period, this paper also provides a hardware architecture for the proposed method and its realization in field programmable gate array. The simulation results show that the proposed methods can achieve lower complexity CS-based channel estimation with almost the identical system performance with the conventional method. Moreover, the realized hardware can achieve the fastest execution time compare to that of other existing methods.

고해상도 영상의 효과적인 처리를 위한 블록 버퍼 기반의 저 복잡도 무손실 프레임 메모리 압축 방법

본 논문에서는 고해상도 영상의 효과적인 처리를 위한 블록 버퍼 기반의 저 복잡도 무손실 프레임 메모리 (frame memory) 압축 방법을 제안한다. 제안하는 압축 방법은 공간적 상관도를 제거하기 위하여 블록단위 MHT (modified Hadamard transform)를 사용하고, 엔트로피 부호화를 위하여 AGR (adaptive Golomb-Rice) 부호화 기법을 적용하여 저 복잡도 무손실 압축 및 효과적인 하드웨어 구현을 달성한다. MHT는 가산기와 1비트 오른쪽 시프트(1-bit right shift) 연산만으로 구성되어 있고, AGR은 별도의 메모리 공간 및 메모리 접근 동작(memory access operation)을 포함하지 않아 저 복잡도 구현이 용이하다. 기존의 저 복잡도 무손실 압축 방법과 비교하여 제안한 알고리즘은 압축률 측면에서 우수한 성능을 나타내고, 기존 코덱(codec)의 구조를 크게 수정하지 않으면서 화질의 열화없이 하드웨어 장치에 적용될 수 있음을 다양한 영상에 대한 실험 및 복잡도 분석을 통해 보인다. 또한 제안한 방법은 메모리 접근 동작을 필요로 하지 않아 하드웨어 구현을 위한 비용을 최소화 할 수 있어, Fill HD급 이상의 고해상도 영상을 효과적으로 처리하는데 유용하다. This study addresses a low complexity and lossless frame memory compression algorithm based on block-buffer structure for efficient high resolution video processing. Our study utilizes the block-based MHT (modified Hadamard transform) for spatial decorrelation and AGR (adaptive Golomb-Rice) coding as an entropy encoding stage to achieve lossless image compression with low complexity and efficient hardware implementation. The MHT contains only adders and 1-bit shift operators. As a result of AGR not requiring additional memory space and memory access operations, AGR is effective for low complexity development. Comprehensive experiments and computational complexity analysis demonstrate that the proposed algorithm accomplishes superior compression performance relative to existing methods, and can be applied to hardware devices without image quality degradation as well as negligible modification of the existing codec structure. Moreover, the proposed method does not require the memory access operation, and thus it can reduce costs for hardware implementation and can be useful for processing high resolution video over Full HD.

On Fixed-Point Implementation of Log-MPA for SCMA Signals

In this letter, we present a design framework for fixed-point implementation of the log-domain message passing algorithm (Log-MPA) for sparse code multiple access signals, and make a detailed comparative analysis on the complexity of Log-MPA and traditional MPA. We also investigate the impact of the number of massage-passing iterations within the Log-MPA decoding process on the performance of Log-MPA. Simulation results demonstrate that Log-MPA achieves favorable performance with low-complexity hardware implementation as compared to MPA. We also implement Log-MPA on FPGA evaluation board to verify the performance of Log-MPA.

Design of Allpass Variable Fractional Delay Filter with Powers-of-Two Coefficients

In this letter, we develop an algorithm for the design of allpass variable fractional delay filter with powers-of-two coefficients as a means of achieving low complexity and efficient hardware implementation. The algorithm includes an efficient procedure to obtain the objective function in the neighborhood of a search point, which significantly reduces the complexity associated with the global optimization approach. Design examples show that significant improvement is obtained by using the proposed method over existing methods.

Low-complexity optical phase noise suppression in CO-OFDM system using recursive principal components elimination.

A low-complexity optical phase noise suppression approach based on recursive principal components elimination, R-PCE, is proposed and theoretically derived for CO-OFDM systems. Through frequency domain principal components estimation and elimination, signal distortion caused by optical phase noise is mitigated by R-PCE. Since matrix inversion and domain transformation are completely avoided, compared with the case of the orthogonal basis expansion algorithm (L = 3) that offers a similar laser linewidth tolerance, the computational complexities of multiple principal components estimation are drastically reduced in the R-PCE by factors of about 7 and 5 for q = 3 and 4, respectively. The feasibility of optical phase noise suppression with the R-PCE and its decision-aided version (DA-R-PCE) in the QPSK/16QAM CO-OFDM system are demonstrated by Monte-Carlo simulations, which verify that R-PCE with only a few number of principal components q ( = 3) provides a significantly larger laser linewidth tolerance than conventional algorithms, including the common phase error compensation algorithm and linear interpolation algorithm. Numerical results show that the optimal performance of R-PCE and DA-R-PCE can be achieved with a moderate q, which is beneficial for low-complexity hardware implementation.

Variable fractional delay filter design with discrete coefficients

This paper investigates the optimal design of variable fractionaldelay (VFD) filter with discrete coefficients as a means ofachieving low complexity and efficient hardware implementation. Thefilter coefficients are expressed as the sum of signed power-of-two(SPT) terms with a restriction on the total number of power-of-twoterms. An optimization problem with least squares criterion isformulated as a mixed-integer programming problem. An optimalscaling factor quantization scheme is applied to the problemresulting in an optimal scaling factor quantized solution. Thissolution is then improved further by applying a discrete filledfunction, that has been extended for a mixed integer optimizationproblem. To apply the discrete filled function method, it requiresmultiple calculations of the objective function around theneighborhood of a searched point. Thus, an updating scheme isdeveloped to efficiently calculate the objective function in aneighborhood of a point. Design examples demonstrate theeffectiveness of the proposed optimization approach.

Design of Robust Broadband Beamformers With Discrete Coefficients and Least Squared Criterion

This brief investigates the performance of robust and nonrobust broadband beamformers with least squares and discrete coefficients to achieve low complexity and efficient hardware implementation. The broadband beamformer coefficients are expressed as the sum of power-of-two terms with a restriction on the total number of power-of-two terms for the beamformer coefficients. An iterative algorithm is employed to reduce the number of nonzero coefficients and, thereby, multipliers in both the robust and nonrobust beamformers. A quantization scheme in combination with a random search is then applied to efficiently distribute the power-of-two terms for the beamformer coefficients. Design examples show that the number of nonzero coefficients for the beamformers can be significantly reduced without a significant degradation in the integral squared error. In addition, robust beamformers are shown to be less sensitive to nonzero coefficient reduction and quantization than nonrobust beamformers.

Power Efficient Sum of Absolute Difference Algorithms for video Compression

Video Compression (VC) is one of the resource hungry key element in video communication and is commonly achieved using Motion Estimation (ME). In this paper we proposed power efficient one bit full adder and one of the simple and easy metric called Sum of Absolute Difference (SAD) for estimating the motion vectors in motion estimation. SAD is primarily used to detect motion in the video sub system. Here we proposed power efficient 4X4 and 8X8 SAD architectures. The proposed 4X4 SAD proves that 29%, 63.23% and 61.31% improvement in leakage power, dynamic power and total power respectively as compared with existing 4X4 SAD. Similarly the proposed 8X8 SAD which proves that 57%, 46.16% and 46.78% improvement in Leakage Power (LP), Dynamic Power (DP) and Total Power (TP) respectively as compared with that of existing 8X8 SAD at the gate level. The designs are implemented in ASIC methodology using cadence tools. Keywords - SAD, ME, VC, CSA, DSP, LP, DP, TP, FPGA etc. I. INTRODUCTION Many recent multimedia applications of digital video systems such as video conferencing, video-on- demand, video-phone, distance learning and digital TV, object tracking and many more have become popular products because of their convenience. Such applications require video compression with ever higher compression ratios, better visual quality and high bandwidth. The high efficiency video compression commonly uses the efficient hardware architectures. In general the development of hardware architectures are designed to form the integrated circuits which allows parallel processing of data from various sub blocks of the architectures, however hardware architectures suffers from limitations such as algorithm flexibility due to timing dependencies, which arises from the dataflow of various blocks of the architecture. Thus the development of good architecture of video codec in integrated circuits is very important. The customization of video codec is the video compression in the modern state of the art real time Digital Signal Processing (DSP) systems. Video compression is one of the techniques in video processing system to reduce resource usage. The two primary challenges addressed during video compression are:  Limited Network bandwidth.  Limited Storage capacity. Hence the two important metrics of a video encoder are low computational complexity & low power hardware implementation. Present day world, compression ratio plays the major role in the field of video processing. The motion in the video scene will reduce the efficiency of the compression ratio. Hence the motion estimation field has seen the highest research topic and interested issue in the past a few decades. In short the motion estimation means the estimation of the displacement (or velocity) of image structures from one frame to another in a time sequence of 2-D images of the video in order to achieve video compression in video coding. The efficiency of the compression ratio can be increased by exploiting the similarities between the video frames. The simple metric system is the SAD algorithm, where the absolute differences between the corresponding elements are added up. There are varieties of video coding standards in the video processing systems; the modern video coding standard is H.264/AVC. This coding standard uses the Variable Block Size Motion Estimation (VBSME), in this standard; the computation requirements are much higher than the previous coding standards such as H.263/ MPEG-IV. In H.264/AVC, each picture frame is divided into many macro blocks.