Lot Acceptance Testing Research Articles

A Comparison of Board-Level Lot Acceptance Testing Method with Worst-Case Analysis Results

A Comparison of Board-Level Lot Acceptance Testing Method with Worst-Case Analysis Results

Lot acceptance testing using sample mean and extremum with finite qualification samples

In the aerospace composites industry, new material lots are tested to determine if they are suitable for use. It is common to accept or reject the material lot by comparing the sample mean and lower extremum to reference values that are established based on an initial (qualification) sample of material property measurements. Current industry practices assume that the samples are drawn from a normal distribution with known parameters equal to the mean and standard deviation of the qualification sample: this assumption yields a producer’s risk that is too high. This article presents a two-sample method of setting these reference values, considering the sampling distribution of the qualification sample. This new method is validated through simulation which shows that it produces the correct probability of Type I error. Simulation is also used to investigate the statistical power of the new method and it is compared to others commonly used. A case study is presented to demonstrate the use of the new method using composite material data from industry.

Enhanced Lot Acceptance Testing Based on Defect Counts and Posterior Odds Ratios

Optimal defects-per-unit test plans based on posterior odds ratios are developed for the disposition of product lots. The number of nonconformities per unit is modeled by the Conway–Maxwell–Poisson distribution rather than the typical Poisson model. In essence, a submitted batch is conforming if its posterior acceptability is sufficiently large. First, a useful approximation of the optimal test plan is derived in closed form using the asymptotic normality of the log ratio. A mixed-integer nonlinear programming problem is then solved via Monte Carlo simulation to find the smallest number of inspected items per lot and the maximum tolerable posterior odds ratio. The methodology is applied to the manufacturing of paper and glass. The suggested sampling plan for lot sentencing provides the specified protections to both manufacturers and customers and minimizes the needed sample size. In terms of inspection effort and accuracy, the proposed approach is virtually an advantageous extension of the classical frequentist perspective. In many practical cases, it yields more precise assessments of the current consumer and producer risks, as well as more realistic decision rules.

Lot acceptance and compliance testing based on the sample mean and minimum/maximum

A dual acceptance criterion in terms of the sample mean and an extremum (minimum or maximum) has been used in many inspection procedures in diverse industries. An approximation is given in Vangel (Technometrics, 2002, pp. 242–248) for the joint distribution of the sample mean and an extremum when the population is normally distributed. In this paper we obtain a simple expression that depends on the distribution of the sample mean and the truncated sample mean. This expression allows us to evaluate the joint distribution exactly, in two cases, or approximately, in more general cases, making the dual acceptance criterion easier to calculate in practice. We present a saddlepoint approximation for the joint tail probability, with the application to the dual acceptance criterion under the assumption of normality.

Lot Acceptance and Compliance Testing Using the Sample Mean and an Extremum

In industry, one sometimes compares a sample mean and minimum, or a mean and maximum, to reference values to determine whether a lot should be accepted. Particularly prominent examples of such procedures are “Category B” sampling plans for checking the net contents of packaged goods. Because the exact joint distribution of an extremum and the mean of a sample is usually complicated, establishing these reference values using statistical considerations typically involves crude approximations or simulation, even under the assumption of normality. The purpose of this article is to use the saddlepoint method to develop a fairly simple and very accurate approximation to the joint cumulative distribution function (cdf) of the mean and an extremum of a normal sample. This approximation can be used to establish statistically based acceptance criteria or to evaluate the performance of sampling plans based on criteria derived in other ways. These uses are illustrated with examples.

Strategies for lot acceptance testing using CMOS transistors and ICs

Direct-correlation and simple overstress methods for estimating IC response in strategic and space environments from laboratory transistor and IC data are investigated. Transistors and ICs were irradiated at dose rates from 0.2 rad(SiO/sub 2/)/s to 10/sup 6/ rad(SiO/sub 2/)/s. Over a wide range of process conditions and hardness levels, laboratory measurements of threshold voltage shift due to oxide trapped charge correlate well with IC leakage current at high dose rates for ICs with gate-oxide-dominated response. For ICs whose response is dominated by parasitic field-oxide structures, laboratory measurements of both transistor and IC leakage currents correlate well with IC hardness at high dose rates. For dose levels up to approximately=500 krad(SiO/sub 2/), it is shown that a simple factor-of-three overtest can be used as a conservative estimate of radiation hardness for strategic applications, provided that both functional and parametric testing is performed following X-ray irradiation at a dose rate of approximately=2000 rad(SiO/sub 2/)/s. For space environments, a laboratory irradiation to 1.5 times the required system level followed by a one-week 100 degrees C biased anneal gave conservative estimates of IC hardness. >

Lot uniformity and small sample sizes in hardness assurance

Recent standard radiation test procedures allow wafer-level lot acceptance testing using as few as two or four parts with no failures. Such tests guarantee a high survivability of the accepted part only when the parts within a wafer exhibit a highly uniform response to radiation and when a large fraction of the wafers pass the test. The author points out the need for validating these tests, suggests techniques for doing so, and recommends modifications to current test procedures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Using laboratory X-ray and cobalt-60 irradiations to predict CMOS device response in strategic and space environments

The postirradiation response of CMOS transistors with 30-60-nm gate oxides is investigated as a function of radiation energy, total dose, dose rate, and annealing time. Measurements of threshold voltage, oxide-trapped charge, and interface traps are reported for times ranging from 10 ms to 4 months following LINAC, Co-60, Cs-137, and 10-keV X-ray irradiations. Exposure dose rates vary by 11 orders of magnitude: from 0.05 to 6*10/sup 9/ rad(SiO/sub 2/)/s. To within the +or-10% uncertainty in the overall dosimetry, no 'true' dose-rate effects on MOS device response are observed. Interface trap and oxide-trapped charge densities are linear with total dose. Preliminary recommendations are made for lot acceptance testing of hardened CMOS circuits and devices intended for use in space and strategic environments.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hardness Assurance Statistical Methodology for Semiconductor Devices

A statistical method is developed for determining electrical end-point limits for semiconductor devices subjected to radiation stress. The approach utilizes multiple lot radiation data and can be applied where lot-to-lot variations in radiation response are large compared to variations within a lot. Such limits may be used as design parameter limits or as failure limits for lot acceptance testing of future hardness-assured, semiconductor production lots. The method was applied for neutron and total gamma dose effects on low power bipolar transistors, digital TTL ICs, and a power transistor for which an adequate multiple-lot radiation database existed.