Strategies for lot acceptance testing using CMOS transistors and ICs

Abstract

Direct-correlation and simple overstress methods for estimating IC response in strategic and space environments from laboratory transistor and IC data are investigated. Transistors and ICs were irradiated at dose rates from 0.2 rad(SiO/sub 2/)/s to 10/sup 6/ rad(SiO/sub 2/)/s. Over a wide range of process conditions and hardness levels, laboratory measurements of threshold voltage shift due to oxide trapped charge correlate well with IC leakage current at high dose rates for ICs with gate-oxide-dominated response. For ICs whose response is dominated by parasitic field-oxide structures, laboratory measurements of both transistor and IC leakage currents correlate well with IC hardness at high dose rates. For dose levels up to approximately=500 krad(SiO/sub 2/), it is shown that a simple factor-of-three overtest can be used as a conservative estimate of radiation hardness for strategic applications, provided that both functional and parametric testing is performed following X-ray irradiation at a dose rate of approximately=2000 rad(SiO/sub 2/)/s. For space environments, a laboratory irradiation to 1.5 times the required system level followed by a one-week 100 degrees C biased anneal gave conservative estimates of IC hardness. >