Long-channel MOS Transistor Research Articles

Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion

This brief studies the current mismatch of MOS transistors operating in weak inversion region. Explicit formulas are derived from the drain-current relationship of a long-channel MOS transistor. By referring the drain-current variance to the gate terminal under the small-signal conditions, the dependence of the gate–source voltage on the design parameters and sources of mismatch can be considered. This will help designers to choose the optimum sizes and the efficient $gm/I_{\text {D}}$ ratio for current offset reduction of transistors that their mismatch affects the circuit performance, significantly. In order to confirm the accuracy of the calculated drain-current variance, the hand analysis results are compared with MATLAB simulator outputs. In addition, the input offset of a conventional folded-cascode amplifier is estimated by hand analysis, and the results are compared with SPICE simulator outputs through Monte Carlo analysis.

Theory of thermal noise in long-channel MOS transistors operating before saturation

This article reports a reinvestigation of the existing thermal noise theory for long-channel MOS transistors, which is shown to have serious flaws as a thermal noise theory. We conclude that the spectral intensity of the channel thermal noise current for a long-channel MOSFET, operating before saturation at both strong and weak inversions, is best given by applying a new theory, which we refer to as the steady-state Nyquist theorem for one-dimensional devices. We also show that a general three-dimensional approach for calculation of the short-circuit thermal noise currents in semiconductor devices supports the new theory. Clear and definitive experimental evidence in support of the steady-state Nyquist theorem is provided.

A generalized tanh law MOSFET model and its applications to CMOS inverters

A generalized tanh law model is proposed to simulate the current-voltage characteristics of both long-channel and short-channel MOS transistors. The proposed model is used to calculate the propagation delay, short-circuit power dissipation, and logic threshold voltage of CMOS inverters. The results obtained are in good agreement with those obtained using classical models. >

Comparison of symmetrical and asymmetrical hot-electron injection in MOS transistors

The effect of nonuniform injection and trapping on the characteristics of long-channel MOS transistors is investigated. Long-channel transistors are symmetrically injected with carriers introduced from adjacent diode stripes which are parallel to the length of the transistor. Asymmetrical injection is performed by introducing carriers from diodes which are closer to the drain of the device under test. The rate of change in the extrapolated threshold voltage is higher for asymmetrical injection, since the same amount of injected charge is submitted to a smaller portion of the channel region. The maximum transconductance rises over the period of stressing for the asymmetrical injection situation, while the transconductance consistently decreases with stress time for symmetrical injection.

A review of long-channel MOS transistor models

Since the long-channel behaviour of MOS devices can be retained in spite of a severe reduction of the MOS transistor channel length, there are still many applications for long-channel MOS transistor models. This paper is a review of such models and its aim is to elucidate the influence of two effects: the dependence of the surface potential on the gate voltage in the strong inversion and mobility modulation along the channel due to the effective transverse electric field variation. The paper contains also a brief discussion of quantum-mechanical effects and mobility modelling.

Modeling of the MOSFET inversion charge and drain current, in moderate inversion

The widespread use of MOS technology in analog circuit design demands a precise and efficient circuit simulation model of the MOS transistor valid in all regions of inversion. Currently available circuit simulation models fail in the intermediate range of gate voltages, known as the moderate inversion region. Expressions characterizing the large-signal behavior of the long-channel MOS transistor in the moderate inversion region are derived. The correct dependencies on all the physical and process parameters are preserved by a careful approximation to the physical equations, based on the charge sheet assumption. Another goal is to develop expressions that treat the moderate inversion as a small, voltage-dependent correction to currently existing simplified models. This approach should allow a simple modification of the existing circuit simulation models to improve the accuracy in moderate inversion. The model was compared with a numerical charge sheet model and with experimental measurements of a long-channel, ion-implanted NMOS transistor. The expressions could serve as a basis for a comprehensive MOSFET circuit simulation model.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Short-channel effects on MOS transistor capacitances

A high-precision capacitance measurement method was applied to long-channel and short-channel MOS transistors. The capacitance characteristics of short-channel transistors were found to deviate significantly from their long-channel counterparts. The velocity saturation effect, vertical-field mobility- degradation effect, channel-length modulation effect, source-and-drain series resistance effect, and channel-side fringingfield have to be taken into account in modeling the small-geometry transistors. Modeled results including the short-channel effects showed good agreement with the measured results.

A small signal dc-to-high-frequency nonquasistatic model for the four-terminal MOSFET valid in all regions of operation

This paper presents a four-terminal small-signal dc-to-high-frequency model, valid in weak, moderate, and strong inversion regimes, for the intrinsic part of the long-channel MOS transistor. A charge-sheet approximation is used. Basic MOSFET equations are separated into parts corresponding to dc and ac small-signal components. The former are used to evaluate the drain current under dc conditions; the latter, describing the "transmission-line" behavior of the MOSFET, are solved to arrive at a complete set of admittance parameters. Based on different approximations of these parameters, various models are presented, each of different upper frequency limit of validity. For each model parameter, a single continuous expression is used which is valid in all regions of operation (weak inversion, moderate inversion, strong inversion; nonsaturation and saturation). The frequency range of validity of these models and the inadequacies of the quasistatic models at high frequencies are discussed. It is shown that at low frequencies the high-frequency model reduces to a quasistatic model which is widely verified by experimental results; at high frequencies the model agrees with available measurements.

Analysis of the depletion-mode MOSFET including diffusion and drift currents

A four-terminal model for a long-channel depletion-mode MOS transistor including both the diffusion and the drift components of the current along the channel is developed. The theory, which is derived in the gradual channel hypothesis, has been built-up by considering both Poisson's equation and the current-continuity equation. The model is able to describe, without discontinuities, the dc drain current in the enhancement, depletion, and subpinchoff regimes of operation of the device. It is shown that pinchoff and zero drain conductance are naturally achieved as the drain voltage increases, while in the subpinchoff regime the drain current exponentially depends on gate voltage and is mainly due to the diffusion component. Finally, it is found that mobility degradation effects due to the normal component of the electric field can easily be taken into account and it is shown that experimental data favorably compare with the proposed model.

A CAD-Oriented Analytical MOSFET Model for High-Accuracy Applications

Explicit and accurate formulations for the surface potential against quasi-Fermi potential of the minority carriers in a long-channel MOS transistor are found. Moreover, it is shown that, for a variety of process parameters, these simple formulations, together with a suitable rearrangement of the Brews' model, can be fruitfully adopted for an accurate modeling of the MOST characteristics in all the operating regimes (weak inversion, moderate inversion, strong inversion).

Modified strong-inversion potential for accurate modelling of long-channel MOS transistors

In long-channel MOS transistor modelling, the classical strong-inversion surface potential ϕS,i (y1=2ϕF+V(y), where ϕF denotes the Fermi potential of the bulk material and V(y) the local potential in the channel with respect to the source electrode, is widely used. It is demonstrated in the paper that this expression for the surface potential in strong inversion may be inaccurate in certain cases, and therefore a new and more accurate strong-inversion surface potential is derived and discussed in connection with a modified long-channel MOS transistor model.

Relation between incremental intrinsic capacitances and transconductances in MOS transistors

The ratio of intrinsic substrate and gate capacitances is related to the ratio of substrate transconductance to gate transconductance for a long-channel MOS transistor in strong inversion. It is shown that under certain assumptions the two ratios are approximately equal.

Large- and small-signal channel transit time delays in long-channel MOS transistors

Turn-on and turn-off delay times (intrinsic channel transit times) of long-channel MOST's are studied for both large-and small-signal inputs. By developing large-signal dynamic equations in normalized form it is evident that the normalized channel current and voltage distributions are unique and independent of device parameters and applied voltages. Channel transit time delays for both large and small signal are found to be given by a simple analytical expression containing a constant, undefined for large signal but defined explicitly for small signal. Values for the constant are found for large- signal operation in several modes by computer simulation representing the channel as a series of cascaded CCD elements. Those for small signal are found by representing the channel as an RC transmission line. With the values of the constant determined, the simple analytical expression is shown to accurately predict channel transit time delays regardless of device type, channel length, width, substrate doping, crystal orientation, or effective mobility. It is concluded that the data presented can be used in designing delay lines or low-pass filters employing long-channel devices.

Long channel MOS transistor (LOMOST) as a current stabilizer

AbstractThe possibilities for current stabilization by means of MOS transistors are investigated. It is shown that with a long enough channel, considerable stabilization can be attained. A coefficient, characterizing the stabilization, is introduced and its dependence on the channel length, Si resistivity and voltage interval is found. The data obtained might be found useful in design of LOMOST current stabilizer with an optimal ratio of the transconductance to the stabilization degree for different purposes.