Logical Effort Research Articles

An Approach to Design a Low Power High-Speed Full Adder Circuit Based on Logical Effort

An Approach to Design a Low Power High-Speed Full Adder Circuit Based on Logical Effort

A methodology of designing and optimising a 4-bit absolute-value detector for the application of Brain-computer Interface

Digital integrated circuits perform logical operations through several modules composed of logic gates. As a common module in digital circuits, the absolute value detector is applied to compare the absolute value of two binary inputs and can be further used for data sorting and searching. In clinical medicine, the detector can receive biological data from the sensor and control the instrument on the operating table. A typical application is Brain-computer Interface (BCI). Therefore, the performance of detectors is significant to electronic devices like computers. The optimisation of detectors usually concentrates on their propagation delay and power consumption. But theoretical optimisation will inevitably use simple logic and have large fan-in, and it is difficult to be implemented in practice. Here we explore an alternative plan that is more convenient to be produced in the industry, which combines static complementary metal-oxide semiconductor (CMOS) technology and transmission gates. After gate sizing, the critical path calculates the propagation delay and energy based on the logical effort theory. Finally, the relationship between energy and delay is analysed by scaling the voltage supply and the minimum energy occurs when the delay grows to 1.5 times the minimum delay.

A New Design of A 6-Bit Absolute Value Detector by Using Both VDD Scaling and Sizing to Optimize

The presented paper focuses on the development and optimization of a 6-bit absolute value detector, a crucial digital block in encoder and decoder applications. The primary objective is to minimize energy consumption while maintaining a delay no greater than 1.5 times the minimum delay. The optimization process combines logical effort theory with gate sizing and voltage scaling techniques. Firstly, gate sizes are adjusted while keeping VDD constant, achieving a 73% reduction in energy consumption, reaching a delay constraint of 1.5 times the minimum delay. Secondly, VDD scaling is explored without altering gate sizes, resulting in a 40% reduction in energy consumption, reaching the minimum energy consumption point. Finally, gate sizing and VDD scaling are combined, yielding a remarkable 79% reduction in total energy consumption, with a supply voltage of 0.835 volts. These optimization strategies bridge a research gap in 6-bit absolute value detectors, significantly enhancing energy efficiency and offering valuable insights for intricate digital signal processing scenarios. The findings showcase the effectiveness of combining logical effort theory with gate sizing and voltage scaling to achieve substantial energy savings while meeting stringent delay constraints.

Design of a 5.94 FO4 absolute-value detector based on hybrid logic technique

With the development of neural signal acquisition systems, spike sorting algorithms have become a hot topic in related fields. The delay of the spike detection system largely determines the speed of the overall signal acquisition system. This paper designs a low-delay Absolute-value Detector based on the GDI technique to improve the timeliness of the neural signal acquisition system. The final circuit has only 20 logic gates-56 transistors. According to the logical effort methodology, the final path delay is 5.94 FO4. This research can provide a reference for the design of future portable ultra-low delay neural signal acquisition systems.

The performance optimization of 4-bit absolute-value detector

Absolute-Value Detection is a popular algorithm used for sorting spiking signals, and the 4-bit Absolute-Value Detector is a fundamental circuit in the spike-sorting field. This paper presents three distinct approaches for designing an absolute-value detector, along with optimization techniques used in these circuits. The paper begins by discussing the circuit’s structure, followed by using logical effort theory to calculate critical path delays. Next, the paper compares the critical path delays and transistor numbers of the three designs. Finally, the paper identifies the optimal design among the three circuits, which provides the best delay performance at a low cost. Applying optimization techniques to the optimal absolute-value detector resulted in a significant improvement in its performance. These findings have important implications for the future development of related industries, as they can help further refine and enhance the performance of spike-sorting algorithms. Overall, this paper provides valuable insights into the design and optimization of absolute-value detectors, which will be of great interest to researchers and practitioners in the field.

The accuracy analysis of different algorithms for 4-Bit absolute value detector

This paper proposes and compares three different algorithms for implementing a 4-bit absolute value detector (AVD) using Complementary Metal Oxide Semiconductor (CMOS) technology. The demand for low power, low delay and high-performance drive the need for AVDs. The proposed algorithms are analysed based on logical effort theory and simulation results for delay and energy performance. The circuits employ a range of logical gates, including multiplexers, NAND gates, XNOR gates, XOR gates, and inverters. The chosen proposed algorithm achieves the lowest delay and energy cost while maintaining high accuracy. Sizing and Vdd optimization can be used to optimize energy, and a 53.7 FO4(1V), 39.91Eu(1V) 4-bit Absolute-Value Detector can be achieved. Overall, this paper provides valuable insights into the design and optimization of AVDs using CMOS technology, which can have important applications in developing electronic systems.

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

We propose a methodology to predict device-level variability (including aging) impact on the oscillation frequency (Fosc) of an N-stage ring oscillator (RO). This task is accomplished by creating a tool in a Python environment that uses our own developed variability-aware timing models of the CMOS inverter. Moreover, we use the model to foretell the impact of aging on the logical effort (g) of a CMOS inverter. Using the modified g, we resize ROs in an RO-based physical unclonable function (PUF) in the pre-layout stage to mitigate the impact of aging on the reliability of RO-PUF. The simulation is performed in the Cadence AMS environment using STMicroelectronics (STM) 28 nm CMOS process technology. With a one-time SPICE/aging simulation, the proposed methodology eliminates SPICE/aging simulation overhead for the prediction of variability impact on Fosc of a given N-stage RO. This approach mitigates the impact of aging on the reliability of RO-PUF and provides a method for variability (including aging) aware design in the pre-layout stage.

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time (t). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre-and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre-and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in Eldo SPICE environment with 65 nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

Design and analysis of a novel fast adder using logical effort method

AbstractAddition, as one of the fundamental math operations, is applied widely in Very‐large‐scale integration systems and digital signal processing, such that the computational speed of a system depends mainly on the computational speed of its adders. There are various types of digital adders based on different methods. A novel adder is proposed which performs addition based on a path with a fewer number of levels, and, hence, with higher computational speed and lower power consumption. The goal and innovation is to design a structured fast adder that has a block that can be expanded to higher bits, and in this design, the calculation speed and power consumption of the proposed circuit are optimal. Each proposed adder circuit has several levels, and the formulae of each level are stated. Each level of the circuit is designed with a number of multiplexers and OR gates. The performance of the proposed adder has been investigated and evaluated in two parts of mathematical calculations and simulation, and it has also been compared with other existing fast adders, such as ripple carry adder, carry skip adder, carry select adder, carry look ahead adder and prefix kogge‐stone in cases of 8, 16, 32 and 64 bits. The results show that the proposed collector has a good performance compared to other adders‐based power consumption, power delay product and delay area product metrics.

Performance Optimization of 4-bit Absolute Value Detector Based on Structural Design

The demand for high-speed electronics is increasing, so this paper presents a new design for a 4-bit absolute value detector, an introductory module in high-speed electronics, using the basic gate circuit except for the transmission gate. This paper introduces the logical effort theory to calculate the worst-case delay of the designed circuit, combines the designed circuit with the relevant equation of the logical effort theory to analyze the delay influencing factors of the circuit, and verifies that the designed circuit achieves the minimum delay to realize the minimum delay design of the basic module. In this paper, the circuit is divided into an absolute value output device and a numerical comparator, but the topology used is a fusion circuit of these two parts, rather than simply connecting the two parts. This study achieves a branch-free circuit while maintaining the condition of minimizing the critical path.

In Silico Stage-Matching of Human, Marmoset, Mouse, and Pig Embryos to Enhance Organ Development Through Interspecies Chimerism

Currently, there is a significant shortage of transplantable organs for patients in need. Interspecies chimerism and blastocyst complementation are alternatives for generating transplantable human organs in host animals such as pigs to meet this shortage. While successful interspecies chimerism and organ generation have been observed between evolutionarily close species such as rat and mouse, barriers still exist for more distant species pairs such as human–mouse, marmoset–mouse, human–pig, and others. One of the proposed barriers to chimerism is the difference in developmental stages between the donor cells and the host embryo at the time the cells are introduced into the host embryo. Hence, there is a logical effort to stage-match the donor cells with the host embryos for enhancing interspecies chimerism. In this study, we used an in silico approach to simultaneously stage-match the early developing embryos of four species, including human, marmoset, mouse, and pig based on transcriptome similarities. We used an unsupervised clustering algorithm to simultaneously stage-match all four species as well as Spearman’s correlation analyses to stage-match pairs of donor–host species. From our stage-matching analyses, we found that the four stages that best matched with each other are the human blastocyst (E6/E7), the gastrulating mouse embryo (E6–E6.75), the marmoset late inner cell mass, and the pig late blastocyst. We further demonstrated that human pluripotent stem cells best matched with the mouse post-implantation stages. We also performed ontology analysis of the genes upregulated and commonly expressed between donor–host species pairs at their best matched stages. The stage-matching results predicted by this study will inform in vivo and in vitro interspecies chimerism and blastocyst complementation studies and can be used to match donor cells with host embryos between multiple species pairs to enhance chimerism for organogenesis.

High-Speed 16-bit Carry Bypass Adder Design

Adders are one of the most significant blocks in a logical arithmetic unit. These are employed in a wide range of applications, from incrementing the value of a program variable to high-speed applications such as video-encoding, digital-signal. There are various adders with varying propagation delays. As a result, selecting an efficient adder is critical for system performance. This research compares the latency of several 16 bit adders that are available. The delay of logic gates in 180nm technology has been quantitatively modelled utilizing logical effort. The delay is then utilized to calculate the delay of various adders in Virtuoso Cadence while simulating. Virtuoso Cadence was used to perform functional verification on adders. Each adder's route delay has also been determined. Based on this research, a new carry bypass adder has been developed to reduce propagation delay. The suggested carry bypass adder reduces combinational path latency by 7.2 percent and logical effort delay by 29.5 percent, respectively. Keywords: Algorithms for 16-bit adders, logical effort, propagation delay, carry skip adder

Exhaust Gas Emissions of Homogeneous Gasoline-Methanol-(Ethanol) Blends

In recent years, one of the most logical efforts made to reduce the dependence on fossil energy sources is the use of a gasoline-methanol fuel blend. However, the problem in using a gasoline-methanol blend as fuel is that the methanol will eventually separate itself from the gasoline unless they are properly blended together, this is because methanol has a polar hydroxyl group called monohydric that binds water vapor together, causing the mixture to separate. Previous research showed that adding a small amount of ethanol to the gasoline-methanol blend makes it a homogeneous blend. Therefore, this research aims to identify the exhaust emissions of the homogenous gasoline-methanol-(ethanol) blend. For each blended fraction was tested on a single-cylinder four-stroke engine. The emission test is carried out in two stages which include the gasoline mode, and the alcohol mode. These two measurement modes undergo a validation process to correct the differences in the measurement results of the gasoline-methanol-ethanol blends. The test results show that increasing the methanol fraction in the gasoline-methanol-(ethanol) fuel blend results in reduced emission of carbon monoxide and unburnt hydrocarbon because methanol has a high enthalpy of evaporation, which increases both volumetric efficiency and complete combustion. In addition, the increase in the methanol fraction in the gasoline-methanol-(ethanol) blend showed a higher increase in carbon dioxide emissions. This is because methanol and ethanol have a much lower energy content than gasoline. Therefore, its energy production per unit time requires more fuel molecules.

Expression of Chimeric HPV-HIV Protein L1P18 in Pichia pastoris; Purification and Characterization of the Virus-like Particles.

Currently, three human papillomavirus (HPV) vaccines are already licensed and all of them are based on virus-like particles (VLPs) of HPV L1 capsid protein but not worldwide accessible. While about 38.0 million people were living with HIV in 2019, only 68% of HIV-infected individuals were accessing antiretroviral therapy as of the end of June 2020 and there is no HIV vaccine yet. Therefore, safe, effective, and affordable vaccines against those two viruses are immediately needed. Both HPV and HIV are sexually transmitted infections and one of the main access routes is the mucosal genital tract. Thus, the development of a combined vaccine that would protect against HPV and HIV infections is a logical effort in the fight against these two major global pathogens. In this study, a recombinant Pichia pastoris producing chimeric HPV-HIV L1P18 protein intracellularly was constructed. After cell disruption, the supernatant was collected, and the VLPs were purified by a combination of ammonium sulfate precipitation, size exclusion chromatography, ultracentrifugation, and ultrafiltration. At the end of purification process, the chimeric VLPs were recovered with 96% purity and 9.23% overall yield, and the morphology of VLPs were confirmed by transmission electron microscopy. This work contributes towards the development of an alternative platform for production of a bivalent vaccine against HPV and HIV in P. pastoris.

Enhanced logic gates and SRAM based on reconfigurable field-effect transistor with asymmetric spacer engineering

In this paper, an early evaluation of reconfigurable field-effect transistor (RFET) with asymmetric spacer engineering in terms of logic cells and static random-access memory (SRAM) is carried out using 3D-TCAD and logical effort theory. The asymmetric underlap channel extension at the drain side (UCED) is demonstrated to be able to increase the on-state saturated current (I ON). Furthermore, the proposed UCED RFET shows great stability for different spacer materials, compared to the conventional RFET. Though a slight deterioration of the normalized delay in UCED RFET, the propagation delay of UCED structure is still smaller due to the lower intrinsic delay in the transistor level because control gate capacitance reduces in the meantime. RFET with asymmetric spacer engineering is also demonstrated to relax the competition between the read and the write operation in SRAM.

Design space exploration of low-power flip-flops in FinFET technology

As technology evolves, new devices emerge to overcome the known short-channel effects of conventional MOSFETs. FinFETs, as recent devices, are widely used in modern processor designs. Elaborate design of circuit elements can effectively increase the overall chip performance. In this paper we studied the design of high performance flip-flop (FF) using FinFET devices. We have investigated several transistor sizing methods in FinFET technology to design the FF circuit based on different input and output capacitances. The results indicate that the circuit designed using minimum-energy-delay-area product (min-EDAP) approach has the lowest PDP. We developed a modified logical effort approach that leads to a minimum EDP design compared to the other approaches. The performance of flip-flop is also investigated based on the metrics extracted from energy efficient curve (EEC). Results show that the ED metric has the minimum EDP in all cases. Moreover, the E4D metric shows the least variations against frequency and voltage fluctuations, while the ED4 metric is more robust against temperature variations. Simulations are performed using HSPICE in 16 nm FinFET technology with shorted-gate (SG) mode configuration.

Performance Analysis of 1 bit HPSC Adder

In the technological evolution of integrated circuits, one of the important and considerable issues is the guesstimate of behavioural analysis of the simple circuits. The simplicity of the theory of logical effort is efficient in the evaluation of timing behaviour of the network with normal CMOS implementation. Howbeit this concept is inefficacious with the hybrid circuits as the circuit structure becomes intricate. At the same time, innumerable circuits with the hybrid arrangement which are good enough in various parameters when compared with standard CMOS have been proposed for various applications. Elite coordinated circuits frequently use adders to accomplish better speed to the detriment of intensity utilization or structure exertion. Hence it is particularly required to comprehend the working of full adders as they thus make an effect in the general gadget execution. The circuits developed by hybrid approach use perceptible logic styles to intensify the performance. Hence there is a great necessity to have an efficient timing behaviour method to determine the proper performance of hybrid adder circuits. This paper presents an efficient investigation that gives the designer a higher level of structure opportunity to focus on a wide scope of utilizations and foresee their exhibition. For the standard and exact selection and reducing of a hybrid adder cell two parameters are taken; one is gain and the other one is the selection factor. These can be quantifiable on the single test bench for the executives of vitality productivity. The predictive analysis is firmly established by implementing in Mentor Graphics for the chosen adder blocks

Delay Minimization in on Chip Interconnects by the Method of Logical Effort

The ultimate aim of the work is to minimize the delay in on-chip interconnects. Our objective is to analyze the wire geometry impact for delay minimization. Here proposed effect is achieved by Logical effort(LE).The analyzes which is on the low swing where it was implemented by using CMOS circuit in 90 nm GPDK library and simulations on the cadence virtuoso ADE EDA tools. Once by reducing the delay the application is oriented for high speed applications. The logical effort (LE) model which reduces the delay minimization. This work which compensates both the long interconnects and short interconnects.

A closed-loop ASIC design approach based on logical effort theory and artificial neural networks

Standard cell library is the backbone of modern day application specific integrated circuit (ASIC) design flow provided by electronic design automation (EDA) vendors worldwide. In these libraries, standard cells are generally available in terms of discrete drive strengths with higher drive strength indicating a faster version of the cell belonging to some predefined logic functionality. However, this leads to increased values of area and power consumption in comparison to a lower drive strength standard cell which has slower response time indicating the underlying tradeoff between speed, area and power. A standard cell with discrete drive strength is not always required during the process of logic synthesis and non-availability of standard cells with fractional drive strengths in the aforementioned libraries hugely impacts the overall performance of resulting digital integrated circuits (ICs) and systems [1]. In this paper, a novel technique has been introduced for on-demand generation and inclusion of standard cells in the logic synthesis process leading to availability of a continuous spectrum of standard cells in terms of drive strengths which ultimately provides a platform for closed-loop ASIC design flow. Logical effort (LE) theory has been utilized alongside artificial neural networks (ANNs) in order to implement the proposed methodology. Extensive circuit simulations have been performed using HSPICE in 130 nm/1.2 V CMOS process technology. Preliminary results are encouraging with up to 41.7% and 62.8% reduction in power-delay product (PDP) and power-delay-area product (PDAP) for a 5-stage gate level test circuit. An 8-bit counter realized using the proposed methodology shows up to 29.77% reduction in power dissipation and 37.8% savings in area at varying capacitive loads when compared to conventional logic synthesis technique which employs a library comprising of standard cells with discrete drive strengths. It is noteworthy that the proposed approach is a general technique which can be easily mapped to high complexity circuits and advanced technology nodes. To support this fact, simulation results have also been provided at 90 nm/1 V CMOS process node for the 5-stage test circuit.

Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures

One of the critical issues in the advancement of very large scale of integration circuit design is the estimation of timing behavior of the arithmetic circuits. The concept of logical effort provides a proficient approach to comprehend and assess the timing behavior of circuits with conventional CMOS (C-CMOS) structure. However, this technique is not working for circuits with a hybrid structure. On the other hand, numerous circuits with the hybrid structure which are faster and consume less power than C-CMOS one have been proposed for different applications such as portable and IoT devices. In this regard, the necessity of having and use of a simple and efficient timing behavior method like conventional logical effort for analysis of the hybrid adder circuits is inevitable. This paper proposes an efficient analysis and modeling technique that enables designers to assess the timing behavior of hybrid full adder circuits at the block level and anticipate their performance in multistage circuits. The gain and selection factor are introduced as a criterion for accurate selection and optimization of the hybrid adder cells measurable on the single test bench for management of energy efficiency and performance tradeoff. The proposed method is investigated using 32-nm CMOS and FinFET technologies.