Logical Effort Research Articles

Stochastic logical effort as a variation aware delay model to estimate timing yield

Considerable effort has been expended in the EDA community during the past decade in trying to cope with the so-called statistical timing problem. In this paper, we not only present a fast and approximate gate delay model called stochastic logical effort (SLE) to capture the effect of statistical parameter variations on the delay but also combine this model with a previously proposed transistor level smart Monte Carlo method to construct ISLE timing yield estimator. The results demonstrate that our approximate SLE model can capture the delay variations and ISLE achieves the same accuracy as the standard Monte Carlo estimator with a cost reduction of about 180×on the average for ISCAS’85 benchmark circuits and in the existence of both inter- and intra-die variations.

A SHORT PROOF THAT NP IS NOT P

This proof of NP 6 P is based on better estimates of lower bounds on the time complexity that hold for all solution algorithms. Almost no special knowledge other than logical and combinatorial efforts is needed to understand the proof.

Logical Effort for CMOS-Based Dual Mode Logic Gates

Recently, a novel dual mode logic (DML) family was proposed. This logic allows operation in two modes: 1) static and 2) dynamic modes. DML gates, which can be switched between these modes on-the-fly, feature very low power dissipation in the static mode and high performance in the dynamic mode. A basic DML gate is very simple and is composed of any static logic family gate and an additional clocked transistor. In this paper, we introduce the logical effort (LE) methodology for the CMOS-based DML family. The proposed methodology allows path length minimization, delay optimization, and delay estimation of DML logic. This is done by development of complete and approximated LE models, which allows easy extraction of design optimization parameters, such as optimum number of stages, gates sizing factors, and delay estimations. The proposed optimization is shown for the dynamic mode of operation. Theoretical mathematical analysis is presented, and efficiency of the proposed methodology is shown in a standard 40-nm CMOS process.

DESIGN OF ALU-64BIT FOR HIGH SPEED USING LOGICAL EFFORT

Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.. Conventional methods use repetitive manual testing guided by Logical Effort (LE).In our work, we choose gate widths inside the circuit as parameters to be optimized in order to achieve the target delay, using LE.The main objective of the paper is to calculate the delay using VerilogHDL and synthesized the output driven by it by increasing the speed using optimized paths.

A comparative analysis of power and delay optimise digital logic families for high performance system design

In this paper, we propose a high performance system design methodology taking the best average delay on prime. Our analysis method is based on the commonly used logical effort methodology, extended to the least delay to find the transistors sizing. Simulation results are tabulated using SPECTRE in 0.18 µm CMOS technology as applied to three different logic styles including static CMOS, pseudo-NMOS and skewed logic. We observe that NAND based pseudo-NMOS logic design having NMOS width as 1 µm exhibits least delay but with enormous power dissipation, evaluated by the tool, whereas, skewed logic style response is better in terms of total power. Thus, the method used accurately shows the trade-off in power-delay of a given circuit, allowing a designer to choose the most appropriate logic style.

Circuit Optimization For Transmission Gate Master Slave Flip-Flops

In this work, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay, power, and area minimization is worthwhile to improve the performance in high-speed designs[1]. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path[1]. Simulations have been performed at transistor level on several well-known TGMS FFs, designed in 65-nm and 90nm technologies using Microwind3.1 CAD tool, and the results have been compared to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements have been found on delay, power and on area occupation, thus showing that this approach allows correctly dealing with the actual path in such circuits and hence to more properly steering the design towards the achievement of efficiency in the high-speed region[1]. epaE� n � �� RGMCET, Nandyal,maheswari.mmr@gmail.comÂ

A Current-Density Centric Logical Effort Delay and Power Model for High-Speed CML Gates

This paper presents a logical effort delay and power model for high-speed current-mode logic (CML) circuits. Current density centric and voltage swing dependent logical effort parameters are defined in terms of the characteristic current density for peak transistor cutoff frequency, which remains relatively constant across different technology nodes. Based on this model, constant and non-constant current density biasing schemes in data-paths of CML circuits are investigated and optimized for delay, power, and energy-delay metrics. The proposed model is simple yet sufficiently accurate for technology nodes in the constant-field scaling regime.

Library-Based Cell-Size Selection Using Extended Logical Effort

Given a synthesized digital integrated circuit comprising interconnected library cells, and assuming arbitrary (continuous) sizes for the cells, experimentally, we have achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power). An accurate table-lookup delay model was developed from the precharacterized industrial standard cell library data by making a formal extension to the concept of logical effort that enables optimization of nMOS and pMOS sizes of a cell separately. To the best of our knowledge, this is the first continuous-cell sizing technique exhibiting optimality based upon a table-lookup delay model. We then developed a new delay-bounded dynamic programming-based algorithm that maps the continuous sizes to the discrete sizes available in the standard cell library, which achieves, for the first time, active area versus delay results close to the continuous results. Parallelism was incorporated into the algorithm to enhance efficiency by leveraging multicore processors. After using state-of-the-art commercial synthesis, the application of our cell-size selection tool results in an active area (the sum of all transistor widths) reduction of 36% (on average) for large contemporary industrial designs.

Design of a novel differential on-chip wave-pipelined serial interconnect with surfing

In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. This uses uniform repeaters (UR). In this paper, two novel surfing techniques, one using uniform repeaters (UR) and another using non-uniform repeaters (NUR) are proposed for differential wave-pipelined serial interconnects. The method of logical effort is also proposed for the design of both UR and NUR. To evaluate the efficiency of these techniques, 40mm metal 4 interconnects using the proposed surfing techniques are implemented along with transmitter, receiver and delay locked loop(DLL) in UMC 180nm technology and their performances are studied through post layout simulations. From this study, it is observed that the differential surfing technique using UR and NUR achieve 3.0 times and 4.15 times higher data rates respectively compared to the single ended scheme whose maximum data rate is 1.33GB/s.

Nand gate architectures for memory decoder

This paper presents some nand gate design styles which when used in decoder reduces energy consumption and delay. Basically conventional, nor style nand, source coupled nand is discussed. The three designs conventional, nor style nand, source coupled nand, ranges in area, speed and power. In nor style nand transistors are added in parallel so high fan-in is obtained and logical effort is reduced. In source coupled nand number of transistors are reduced it give speed of operation compared to an inverter. When simulated and compared it is found that nor style nand is 35% faster and 67 % more power efficient than conventional. Source coupled nand is found to be 36% faster and 82% more power efficient than conventional nand gate.

128 Bit Low Power and Area Efficient Carry Select Adder

Select Adder (CSLA) which provides one of the fastest adding performance. Traditional CSLA require large area and more power. Recently a new CSLA adder has been proposed which performs fast addition, while maintaining low power consumption and less area. This work mainly focuses on implementing the 128 bit low power and area efficient carry select adder using 0.18 µm CMOS technology. Based on the efficient gate level modification, 128-b Square Scheme Block (SSB) CSLA) architecture have been developed and compared with the regular SSB CSLA architecture. The performance of the proposed SSB CSLA evaluated manually in terms of delay, power, and area manually with logical effort and also through custom design. The proposed design has been developed using verilog HDL and synthesized in cadence RTL compile using typical library of TSMC 0.18µm technology.

Low voltage dual mode logic: Model analysis and parameter extraction

The Dual Model Logic (DML) family, which was recently introduced by our group for sub-threshold operation, provides an alternative design methodology to the existing low power digital design techniques. DML gates allow switching between static and dynamic modes of operation on-the-fly according to system requirements, presenting better tradeoff between Energy consumption and performance. In static mode, low voltage DML gates achieve very low Energy consumption with moderate performance, while in dynamic mode they achieve high performance, albeit with higher Energy consumption. In this paper we analyze DML gates operation in the sub- and near-threshold regions by employing a recently proposed transregional model for low supply voltages. The sizing methodology of low voltage DML is discussed and classical Logical Effort parameters are calculated for the 40nm DML basic gates. The design example of a DML full adder, implemented in a 40nm low power standard CMOS technology, is shown to compare the proposed method with its CMOS and Domino counterparts. Monte Carlo simulations are shown to demonstrate the DML immunity to process variations.

A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits

This paper presents a comprehensive comparison between Levenberg-Marquardt (LM) and logical effort (LE) theory-based optimisation techniques. While LM is a classical approach for optimisation and is embedded in SPICE, logical effort-based approach is contemporary, design specific and needs simple back of the envelope calculations for optimisation of digital circuits. Both the approaches have been used by digital circuit designers in the literature for comparing a proposed digital circuit with the existing designs while optimising any given design for timing, power and area parameters. The goal of writing this paper is to make digital system designers gain an insight into the procedures used for optimising digital circuits while at the same time a well-defined approach using LM algorithm is provided that can be easily automated with the current generation CAD tools. For the purpose of comparison some standard circuits were chosen and optimised for minimum PDP and PDAP. SPICE simulations have been extensively used for comparing the two methodologies in a 180 nm\1.8 V CMOS technology.

Automated transistor width optimisation algorithms for digital circuits

This paper presents two novel automated transistor width optimisation algorithms based on Levenberg-Marquardt (LM) algorithm (embedded in SPICE) and logical effort theory proposed by Sutherland et al. (2004). This paper has incorporated the complete logical effort theory from scratch in TCL; hence, it works independent of SPICE tool and can optimise any number of transistors present in circuit. The algorithm can be used as open source optimisation tool and modifications can be done to it according to the need. The proposed algorithms can be utilised for automated library cell characterisation where precise and large numbers of driving strength cells are required. Since the algorithms are automation based, they can play a pivotal role in development of library less synthesis. Optimisations results using proposed algorithms were obtained for both sequential logic blocks (flip-flop) and combinational logic blocks (basic logic gates). Both the algorithms have their own advantages and disadvantages.

Gate-Pitch Optimization for Circuit Design Using Strain-Engineered Multifinger Gate Structures

Optimal transistor sizing and layout using multifinger gate structures (MFGSs) in mechanical stress-engineered CMOS technology is a major issue. We observe that the pull-down and pull-up delay of an inverter using seven-fingered devices with fan-out-of-four (FO4) load increases by ~ 9% and ~ 14%, respectively, compared with the FO4 delay of a reference inverter using single-finger gate structure. On the other hand, doubling gate-pitch in the above inverter improves the pull-down and pull-up delay by ~ 18% and ~ 23%, respectively, compared with the delay of the reference inverter. In this brief, we present a methodology of transistor sizing and layout optimization for MFGSs in stress-engineered CMOS circuits. For this, we derive and validate a modified model of logical effort (LE), where LE is expressed as a function of the number of fingers (NF) and gate-pitch (Lpp). Using our model, we reduce the error in the estimated delay of a four-stage buffer with FO4 from ~ 9% to ~ 1%. Using our methodology, we improve the circuit performance by 7%.

The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices

In this paper we propose a modified model of logical effort for designing optimized buffers in multi-fingered layout scenario in the presence of process induced mechanical stress. It is observed that mechanical stresses induced by tensile and compressive Etch Stop Liner (t-ESL and c-ESL), embedded SiGe (eSiGe) and Shallow Trench Isolation (STI) are not uniform in all the fingers sharing an active region. As a result there is an unaccounted change in the drive current with the number of fingers; thereby causing an unaccounted change in the performance of logic gates implemented using multi-fingered layouts. We explore the impact of mechanical stress induced variability in inverters with multi-fingered devices and derive relationship between the logical effort (LE) and number of fingers (NFs). We use this relationship for predicting CMOS buffer delays more accurately and thus reducing the need for post-layout resizing of their transistors.

Low-Power and Area-Efficient Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops

In this paper we show that, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay minimization is worthwhile to improve the performance in high-speed designs. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path. Simulations are performed on several well-known TGMS FFs, designed in a 65-nm technology, to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements are found on delay and, remarkably, on energy and area occupation, thus showing that this approach allows to correctly deal with the actual path effort in such circuits and hence to more properly steer the design towards the achievement of energy efficiency in the high-speed region.

Tapered-Vth Approach for Energy-Efficient CMOS Buffers

In this paper, “tapered-Vth” buffers are explored as an approach to significantly improve the energy efficiency of traditional CMOS buffers. In this approach, the transistor threshold voltage is progressively increased throughout the buffer stages, in addition to the traditional transistor tapered sizing. Analysis shows that tapered-Vth buffers are able to significantly widen the range of energy-delay trade-offs achievable in real designs, thereby showing improved design flexibility compared to single-Vth buffers. In addition, tapered-Vth buffers are shown to offer an up to 3× energy reduction under a given performance constraint. A circuit-level optimization procedure including the leakage energy contribution is adopted to explore the entire energy-delay space, in contrast to previous analyses that targeted only a specific point. To this aim, an analytical framework to express the energy-delay trade-off of CMOS buffers is presented, based on the Logical Effort methodology. Simulations in a 45-nm CMOS technology are extensively performed to validate the approach in a case study (Word Lines buffers for memory arrays) and in a number of other design cases. Extensive simulations are performed to understand the limits of the proposed approach, as well as the impact of the activity rate, the supply voltage, and process variations.

Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture

Hardware implementation of decimal floating-point arithmetic is a topic of great interest among the researchers in computer arithmetic and also the digital processor industry. Software packages for decimal arithmetic are actually being challenged by decimal hardware units. This spreading trend seems to include hardware implementation of elementary functions. The (Coordinate Rotation Digital Computer) CORDIC algorithm, due to its simplicity, is one of the most efficient methods for computing elementary functions. In this work, we develop a decimal CORDIC scheme with almost half number of equally long cycles with respect to the best previous design. This is achieved via retiming of the conventional CORDIC architecture and selection of the microrotation factors by rounding. However, the proposed design does not lead to a predetermined constant scaling factor. The solution that we use is to iteratively compute the logarithm of the scaling factor followed by a decimal exponentiation. The same CORDIC hardware is reused for performing the latter. The proposed CORDIC method requires 2n + 3 cycles for n-digit decimal operands vs. 4n cycles of the previous methods. Evaluations with 16-digit operands based on logical effort analysis conclude that the proposed architecture shows 82% speed advantage, at the cost of 60% more area and 2.5Â KB more ROM.