The performance optimization of 4-bit absolute-value detector

Abstract

Absolute-Value Detection is a popular algorithm used for sorting spiking signals, and the 4-bit Absolute-Value Detector is a fundamental circuit in the spike-sorting field. This paper presents three distinct approaches for designing an absolute-value detector, along with optimization techniques used in these circuits. The paper begins by discussing the circuit’s structure, followed by using logical effort theory to calculate critical path delays. Next, the paper compares the critical path delays and transistor numbers of the three designs. Finally, the paper identifies the optimal design among the three circuits, which provides the best delay performance at a low cost. Applying optimization techniques to the optimal absolute-value detector resulted in a significant improvement in its performance. These findings have important implications for the future development of related industries, as they can help further refine and enhance the performance of spike-sorting algorithms. Overall, this paper provides valuable insights into the design and optimization of absolute-value detectors, which will be of great interest to researchers and practitioners in the field.