Logic Density Research Articles

Divide and conquer [SoC design

The complexity of chip-level integration has held back the effective logic density of SoC designs - making it difficult to build complex chips, such as high-integration set-top box controllers. That could change as teams adopt methods taking advantage of tools that can deal with logical and physical partitions separately. At the physical level, system-on-chip (SoC) design methods have evolved to increase density and shorten implementation time by improving predictability on timing, routing and design integrity closure. Methods based on physical partitions have taken full advantage of emerging tools and available chip density. The effectiveness of the approach comes from three elements that have been made available recently in back-end tools.

A system approach for partially reconfigurable architectures

The increasing logic density of current Field Programmable Gate Arrays (FPGA) enables the integration of whole systems on one programmable chip. Using concepts of partial dynamic reconfiguration allows the adaptation of complex systems to changing requirements at run-time. In this paper we present a realisable approach for dynamic system integration on Xilinx Virtex FPGAs. In contrast to existing approaches that consider fixed slots for module placement, our approach allows fine-grained placement of modules with variable width along a horizontal communication infrastructure. By simulation we show that the proposed 1D-approach outperforms 2D-approaches by means of the device utilisation and external fragmentation.

A clustering- and probability-based approach for time-multiplexed FPGA partitioning

Improving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an important research topic for reconfigurable computing. Due to the precedence and capacity constraints in TMFPGAs, the clustering and partitioning problems for TMFPGAs are different from the traditional ones. In this paper, we propose a two-phase hierarchical approach to solve the partitioning problem for TMFPGAs. With the precedence and capacity considerations for both phases, the first phase clusters nodes to reduce the problem size, and the second phase applies a probability-based iterative-improvement approach to minimize cut cost. Experimental results based on the Xilinx TMFPGA architecture show that our algorithm significantly outperforms previous works.

Design and implementation of a lossless parallel high-speed data compression system

Logic density increases have made feasible the implementation of multiprocessor systems able to meet the intensive data processing demands of highly concurrent systems. We describe the research and hardware implementation of a high-performance parallel multicompressor chip. A detailed investigation into the performances of alternative input and output routing strategies for realistic data sets demonstrate that the design of parallel compression devices involves important trade offs that affect compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware and is shown to provide a scalable compression solution at throughputs able to cope with the demands of modern high-bandwidth applications.

Statistics of Intuitionistic versus Classical Logics

For the given logical calculus we investigate the proportion of the number of true formulas of a certain length n to the number of all formulas of such length. We are especially interested in asymptotic behavior of this fraction when n tends to infinity. If the limit exists it is represented by a real number between 0 and 1 which we may call the density of truth for the investigated logic. In this paper we apply this approach to the intuitionistic logic of one variable with implication and negation. The result is obtained by reducing the problem to the same one of Dummett's intermediate linear logic of one variable (see [2]). Actually, this paper shows the exact density of intuitionistic logic and demonstrates that it covers a substantial part (more than 93%) of classical prepositional calculus. Despite using strictly mathematical means to solve all discussed problems, this paper in fact, may have a philosophical impact on understanding how much the phenomenon of truth is sporadic or frequent in random mathematics sentences.

The effect of LUT and cluster size on deep-submicron FPGA performance and density

In this paper, we revisit the field-programmable gate-array (FPGA) architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cluster-based island-style FPGAs (Betz et al. 1997) we look at the effect of lookup table (LUT) size and cluster size (number of LUTs per cluster) on the speed and logic density of an FPGA. We use a fully timing-driven experimental flow (Betz et al. 1997), (Marquardt, 1999) in which a set of benchmark circuits are synthesized into different cluster-based (Betz and Rose, 1997, 1998) and (Marquardt, 1999) logic block architectures, which contain groups of LUTs and flip-flops. Across all architectures with LUT sizes in the range of 2 to 7 inputs, and cluster size from 1 to 10 LUTs, we have experimentally determined the relationship between the number of inputs required for a cluster as a function of the LUT size (K) and cluster size (N). Second, contrary to previous results, we have shown that clustering small LUTs (sizes 2 and 3) produces better area results than what was presented in the past. However, our results also show that the performance of FPGAs with these small LUT sizes is significantly worse (by almost a factor of 2) than larger LUTs. Hence, as measured by area-delay product, or by performance, these would be a bad choice. Also, we have discovered that LUT sizes of 5 and 6 produce much better area results than were previously believed. Finally, our results show that a LUT size of 4 to 6 and cluster size of between 3-10 provides the best area-delay product for an FPGA.

Hardware technology for the Hitachi MP5800 series (HDS Skyline Series)

The Hitachi MP5800 series (HDS Skyline Series/sup TM/) has been developed as the top-of-the-line member of the M Parallel Series general computer family. Its highlights include the highest processor performance, dramatically reduced installation requirements (footprint and power consumption), and enhanced reliability and availability. To achieve these goals, innovative technologies have been developed: semiconductor technology called Advanced CMOS-ECL (ACE), which combines high speed emitter coupled logic (ECL) and high density complementary metal oxide semiconductor (CMOS) circuits, one-module processor, which employs a glass ceramic substrate, a high density packaging scheme whereby up to four instruction processors (IPs) are mounted on a single printed wiring board, a cooling technology for large scale integration (LSI) chips with a power consumption as high as 140 W/chip, and a compact high-efficiency power supply system.

Photon‐conserving Radiative Transfer around Point Sources in Multidimensional Numerical Cosmology

Many questions in physical cosmology regarding the thermal and ionization history of the inter- galactic medium are now being successfully studied with the help of cosmological hydrodynamical simu- lations. Here we present a numerical method that solves for the radiative transfer around point sources within a three-dimensional Cartesian grid. The method is energy-conserving independent of resolution; this ensures correct propagation speeds for ionization fronts. We describe the details of the algorithm and compute as a —rst numerical application the ionized region surrounding a mini-quasar in a cosmo- logical density —eld at z 7. Subject headings: cosmology: theorygalaxies: formationgalaxies: ISMintergalactic medium ¨ radiative transfer

Use of multiple‐valued logic with 1.9‐V operational power supply to obtain a high‐speed current‐mode logic circuit

AbstractThis paper proposes a new construction of bipolar current‐mode (CML) logic circuits based on the multiple‐valued logic concept. Applying the multiple‐valued logic concept, the new logic function, which can replace the conventional stack logic circuit and can be operated by a low supply voltage, can be realized. In conventional circuits, it is difficult to generate a signal with multiple voltage levels at the same time as the output of a logic gate and logic gates must be connected by placing a level‐shifter between them.A circuit is devised in this study that generates the multiple‐valued logic levels (three levels in this paper) simultaneously at the output of the logic gate. Also, it is examined whether or not the basic logic functions, such as NAND, NOR, EX‐OR, and D‐Latch, can be realized by the proposed configuration. The characteristics of the proposed circuit are circuit simulated by a SPICE circuit simulator. It is seen as a result that the power consumption, the logic density, and the high‐speed performances, comparable to the conventional stacked‐gate logic circuit, can be realized with the low supply voltage of 1.9 V.

The Triptych FPGA architecture

Field-programmable gate arrays (FPGAs) are an important implementation medium for digital logic. Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints. In this paper we present Triptych, an FPGA architecture designed to achieve improved logic density with competitive performance. This is done by allowing a per-mapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits. We show that, using manual placement, this architecture yields a logic density improvement of up to a factor of 3.5 over commercial FPGAs, with comparable performance. We also describe Montage, the first FPGA architecture to fully support asynchronous and synchronous interface circuits.

Placement and routing tools for the Triptych FPGA

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications.

The WASP3 monolithic-WSI massively parallel processor

The ASP (Associative String Processor) is a massively parallel fault tolerant associative processor designed for the implementation of extensible parallel processing systems. This paper describes the WASP3 processor, which is an implementation of an ASP processor array, comprising a large monolithic silicon device (5.5 cm/spl times/5.5 cm) hybridized with a bonded-silicon High Density Interconnect (HDI), which has been developed to provide a reliable interconnection medium for Wafer Scale Integration (WSI) devices. The HDI supports multi-layer, passive interconnect, providing superior electrical and noise properties for the distribution of power and signal, and allowing the WSI device to achieve improved logic density by reducing monolithic tracking overheads.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Architecture of field-programmable gate arrays

A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed, and several logic blocks used in commercially available FPGAs are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture model. Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture, its routability, and its density are reviewed. >

Flexibility of interconnection structures for field-programmable gate arrays

The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required to achieve good routability is determined by implementing several industrial circuits in a variety of interconnection architectures. These experiments indicate that high flexibility is essential for the connection block that joins the logic blocks to the routing channel, but a relative low flexibility is sufficient for switch blocks at the junction of horizontal and vertical channels. Furthermore, it is necessary to use only a few more routing tracks than the absolute minimum possible with structures of surprisingly low flexibility.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

BiCMOS DCVSL gate

A BiCMOS differential cascode voltage switch logic (DCVSL) gate is presented. The circuit consists of a CMOS differential logic circuit and a bipolar differential sense pair. The result is a high speed CMOS to ECL conversion circuit with relatively high logic density. Simulation results of a test circuit are presented and indicate that this logic gate is competitive with ECL in terms of speed and with CMOS in terms of integration density.

XC3000 family of user-programmable gate arrays

Due to their high density and the convenience of user-programmability, programmable gate arrays are an important new alternative in the ASIC market. Xilinx user-programmable gate arrays, called logic cell arrays (LCAs), are available in sizes ranging from 1200 to 9000 gates. The benefits of the user-programmable gate array are derived from the general-purpose LCA architecture. The LCA architecture features three types of user-configurable elements: an interior array of logic blocks; a perimeter of I/O blocks, and interconnection resources. Configuration is established by programming internal static memory cells that determine the logic functions and interconnections. An IC design and layout methodology based on modularity combined with the use of advanced processing technology allowed this architecture to be extended to 9000 usable gates. Architectural resources were designed to allow for a range of logic densities without compromising overall performance. User-programmable gate arrays can be used in place of conventional, mask-programmed gate arrays for the majority of digital designs.

Alteration in stereological density parameters of the mucosal vascular bed during neoplastic transformation in sublingual keratosis

Stereological techniques have been used to study the vascularity in 110 sublingual keratosis lesions and 22 specimens of normal sublingual mucosa using an image analysis system "IBAS 1". The stereological parameters volume density (Vv), and surface density (Sv) were significantly increased in sublingual keratosis lesions as compared with those of normal sublingual mucosa. Lesions that eventually underwent malignant change showed the highest values and were highly significant (p less than .001) when compared with those which did not do so. The present results demonstrate that vascularity could be a supportive marker of impending malignant change in sublingual keratosis lesions.

Fast two dimensional cluster finding in particle physics

The cluster finding module (CFM) is part of the UA1 trigger processor. The CFM detects and counts two-dimensional clusters of electromagnetic particles. This process requires 75 ns for detection of either isolated or nonisolated clusters and 75 ns to count them. This is equivalent to a peak computational rate of 11000 MIPS (million instructions per second) per module (3000 MIPS average). The required high logic density and speed are achieved by using programmable array logic devices within a pipelined system. The design has been strongly influenced by the need for in-situ computer testing. >

The LT1280 for Through-the-Pins Testing of the Thermal Conduction Module

Testing the thermal conduction module (TCM), the high-density field-replaceable unit (FRU) used in the IBM 3081 processor models, and diagnosing the faults encountered to a minimal repairable set of entities posed a new problem for the IBM engineers. The requirement and the economic necessity of thoroughly exercising the entire TCM logic and random access memory (RAM) array structure through the input/output pins of the TCM are discussed. This is followed by a description of the test system alternatives and the LT1280 [logic tester having 1280 input/output (I/O) pins] as the selected TCM manufacturing test system. The TCM logic density and high I/O count required new concepts of test system organization, size, and complexity to achieve a test and diagnostic system with high flexibility and high throughput capability.

VLSI/LSI Circuit Functions: Their Chanllenges, Rewards, and Problems

Sperry Univac is concluding, the development of a family of very large to large scale integrated (VLSI/LSI) bipolar logic components. These parts supply universal functions in general computer applications and are not unique to a specific system. This approach is, in itself, unique for a computer mainframe manufacturer, since these designs are not proprietary and are meant for off-the-shelf commercial usage. If the volume objectives are met, the price of these components will be attractive to other users, and the components will be used over a broad range of application and speed. A description of the functions, the logic density, the technology, and the circuits used are covered. A comparison of these functions to their small to medium scale integrated (SSI/MSI) components is also discussed. Finally the areas of schedules, costs, and problems encountered are covered.