Complementary Metal Oxide Semiconductor Logic Research Articles

Stable Delocalized Singlet Biradical Hydrocarbon for Organic Field‐Effect Transistors

Delocalized singlet biradical hydrocarbons hold promise as new semiconducting materials for high‐performance organic devices. However, to date biradical organic molecules have attracted little attention as a material for organic electronic devices. Here, this work shows that films of a crystallized diphenyl derivative of s‐indacenodiphenalene (Ph2‐IDPL) exhibit high ambipolar mobilities in organic field‐effect transistors (OFETs). Furthermore, OFETs fabricated using Ph2‐IDPL single crystals show high hole mobility (μh = 7.2 × 10−1 cm2 V−1 s−1) comparable to that of amorphous Si. Additionally, high on/off ratios are achieved for Ph2‐IDPL by inserting self‐assembled mono­layer of alkanethiol between the semiconducting layer and the Au electrodes. These findings open a door to the application of ambipolar OFETs to organic electronics such as complementary metal oxide semiconductor logic circuits.

III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si.

III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I(on)/I(off) ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.

A study on room-temperature photoluminescence and crystallinity of RF-sputtered GaN for a cost-effective III-V-on-Si platform

Recently, Si technology has been searching for ways to develop Si-driven future electronics by overcoming the limitations in its electrical and optical properties through more Moore (MM), morethan- Moore (MtM), and beyond complementary metal-oxide-semiconductor (CMOS) approaches. Among the suggested strategies, III-V-on-Si heterogeneous integration can be a solution that allows the merger of III-V-based devices and Si CMOS logic blocks on Si monolithically and costeffectively. GaN has wide applicability owing to its high electron mobility and large energy bandgap for high-speed low-power transistors and visible light sources. In this work, the room-temperature photoluminescence (PL) characteristics and the crystallinity of GaN-on-Si were empirically studied. GaN was deposited by using RF sputtering on p-type Si substrates. The results show that the peak location near 520 nm does not vary with the wavelength of the excitation laser, which is strongly supported by the fact that the signals are not from higher-order harmonics but are genuinely from the prepared GaN. Further, a sharp peak is observed in the X-ray diffraction (XRD) analysis cooperatively performed with PL experiments. Consequently, partially-crystallized GaN has been obtained on Si by using conventional CMOS processing with a low thermal budget and high cost-effectiveness.

Mechanically Flexible and High-Performance CMOS Logic Circuits.

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

Very‐large‐scale integration implementation of a 16‐bit clocked adiabatic logic logarithmic signal processor

This study describes a low-power 16-bit logarithmic signal processor built using clocked adiabatic logic. The circuit has been designed and implemented using an Austria Micro Systems 0.35 μm complementary metal–oxide–semiconductor (CMOS) process. A test device has been fabricated and functionally verified. The processor architecture has an active area of 0.57 mm2. Simulation results with this architecture, using clock frequencies up to 100 MHz have confirmed results from other researchers that clocked adiabatic consumes up to ten times less power than conventional CMOS logic.

Heteroepitaxial Ge MOS Devices on Si Using Composite AlAs/GaAs Buffer

Structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated. Electrical characteristics of N-type metal-oxide-semiconductor (MOS) capacitors, fabricated from the aforementioned material stack are then presented. Simulated and experimental X-ray rocking curves show distinct Ge, AlAs, and GaAs epilayer peaks. Moreover, secondary ion mass spectrometry, energy dispersive X-ray spectroscopy (EDS) profile, and EDS line profile suggest limited interdiffusion of the underlying buffer into the Ge layer, which is further indicative of the successful growth of device-quality epitaxial Ge layer. The Ge MOS capacitor devices demonstrated low frequency dispersion of 1.80% per decade, low frequency-dependent flat-band voltage, $V_{FB}$ , shift of 153 mV, efficient Fermi level movement, and limited C-V stretch out. Low interface state density $(D_{it} )$ from $8.55 \times 10^{11} $ to $1.09 \times 10^{12}~ {\rm cm}^{-2} ~{\rm eV}^{-1} $ is indicative of a high-quality oxide/Ge heterointerface, an effective electrical passivation of the Ge surface, and a Ge epitaxy with minimal defects. These superior electrical and material characteristics suggest the feasibility of utilizing large bandgap III-V buffers in the heterointegration of high-mobility channel materials on Si for future high-speed complementary metal-oxide semiconductor logic applications.

Optical properties and electronic band lineup on Si of amorphous zirconium modified Bi2Zn2/3Nb4/3O7 thin films

We have investigated optical and band alignment properties of pulsed laser deposited amorphous thin films of bismuth based monoclinic pyrochlore Bi2Zn2/3−x/3Nb4/3−2x/3ZrxO7 (Zr–BZN) where x=0.4 on quartz and silicon substrates, respectively. The optical parameters, such as complex refractive index (n−jk), energy bandgap (Eg), complex dielectric function (ε′-jε″), and complex conductivity (σ′-jσ″) and associated dispersion parameters were estimated from the UV–Visible transmission spectra. The analysis of refractive index dispersion confirmed the Wemple–DiDomenico single-effective-oscillator model for the direct inter-band transition. The valence band of Zr–BZN is found to be ∼0.1eV above that of silicon. The numerical values for conduction band offset ΔEC on silicon and optical bandgap Eg were estimated to be ∼2.46eV and ∼3.46eV, respectively for Zr–BZN samples. We determined a complete electron band offset dominated type II staggered band lineup of this high-k dielectric/semiconductor heterostructure, where a straight forward spatial confinement of electrons and holes is facilitated. These important results can play critical role and provide key insight for the practical applications of Zr–BZN material, especially in CMOS (complementary metal–oxide–semiconductor) logic and memory devices.

A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

In this letter, a phase change random access memory (PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor (CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 mA, 100 and 10 ns, respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

SummaryIn this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley &amp; Sons, Ltd.

Design of a Low‐Power 20Gb/s 1:4 Demultiplexer in 0.18μm CMOS

A low-power multi-phase clock 20Gb/s 1:4 Demultiplexer (DEMUX) without inductors is designed in 0.18μm Complementary metal oxide semiconductor (CMOS) process. The 1:4 DEMUX includes two 1:2 DEMUX cells, one 1/2 frequency divider cell, some data and clock buffers. A dynamic CMOS logic latch is used in the 1:2 DEMUX cell and a single clock dynamic-loading latch is used in the 1/2 frequency divider cell. These two kinds of logical structures not only reduce power dissipation and area, but also have an output rail-to-rail level. The rail-to-rail level can offer high noise margin and implement seamless connection without logic level conversion in system integration. The test results show that when the data rate of the input pseudorandom is 20Gb/s and the sequence length is 231-1, this 1:4 DEMUX can work well at a supply voltage of 2V. The output swing is 450mV with external 50 Ohm load and the die size is 0.475×0.475 mm2. The chip power dissipation is 86mW, when four pads connect with a four-channel oscillograph.

Silicon‐Based Current‐Controlled Reconfigurable Magnetoresistance Logic Combined with Non‐Volatile Memory

Silicon‐based complementary metal‐oxide‐semiconductor (CMOS) transistors have achieved great success. However, the traditional development pathway is approaching its fundamental limits. Magnetoelectronics logic, especially magnetic‐field‐based logic, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Existing proposals of magnetic‐field‐based logic are based on exotic semiconductors and difficult for further technological implementation. Here, a kind of diode‐assisted geometry‐enhanced low‐magnetic‐field magnetoresistance (MR) mechanism is proposed. It couples p‐n junction's nonlinear transport characteristic and Lorentz force by geometry, and shows extremely large low‐magnetic‐field MR (&gt;120% at 0.15 T). Further, it is applied to experimentally demonstrate current‐controlled reconfigurable magnetoresistance logic on the silicon platform at room temperature. This logic device could perform all four basic Boolean logic including AND, OR, NAND and NOR in one device. Combined with non‐volatile magnetic memory, this logic architecture with unique magnetoelectric properties has the advantages of current‐controlled reconfiguration, zero refresh consumption, instant‐on performance and would bridge the processor‐memory gap. Our findings would pave the way in silicon‐based magnetoelectronics and offer a route to make a new kind of microprocessor with potential of high performance.

5-Gb/s and 10-GHz Center-Frequency Gaussian Monocycle Pulse Transmission Using 65-nm Logic CMOS With On-Chip Dipole Antenna and High-&lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;\(\kappa \) &lt;/tex-math&gt;&lt;/inline-formula&gt; Interposer

Interchip data transmission was demonstrated using impulse radio ultrawideband complementary metal- oxide-semiconductor (CMOS) transmitter integrate circuits with on-chip dipole antennas. A differential pseudorandom binary sequence of 2 7 data of Gaussian monocycle pulse (GMP) was formed by 65-nm CMOS logic circuits using upand downpulses with certain gate delays. The CMOS transmitter generated 5-Gb/s GMP with the center frequency of 10 GHz. To improve transmission gains, an interposer with the high dielectric constant (e r = 38) and optimized thickness was inserted under the CMOS chips as a dielectric slab waveguide. 2-Gb/s GMP signals were transmitted and received in the distance of 10 mm by use of the CMOS on-chip antennas and the high-κ interposer.

Slow is the new fast (and other stories from the cutting edge of chip tech...)

The power used by the CMOS (complementary metal-oxide semiconductor) logic that sits in practically all microprocessors is controlled by a formula that links the square of the voltage to the frequency at which the transistors switch. Because of the quadratic relationship, lowering the voltage has a dramatic effect on energy consumption. Intel is one of a group of companies investigating the potential of near-threshold and sub-threshold logic, where the supply voltage to each transistor is reduced to the point where it barely switches on. The technology takes advantage of the way in which small amounts of current pass through the transistor as it moves from the off state to the on. This is enough to charge the capacitances in downstream logic that help move from one state to another. However, with less current passing, the longer the entire process takes. A chip that happily operates at gigahertz frequencies at 1V has trouble switching at more than one megahertz when that voltage falls towards the threshold point, at around 0.25V for the latest process technologies; and yet, this is something that chip designers are willing to work with.

Three-dimensional confocal imaging for breast cancer detection using CMOS Gaussian monocycle pulse transmitter and 4 × 4 ultra wideband antenna array with impedance matching layer

A time-domain reflectometry breast cancer detection system was developed, which was composed of a Gaussian monocycle pulse (GMP) transmitter circuit fabricated by complementary metal oxide semiconductor (CMOS) 65 nm technology and an ultra wide-band (UWB) planar slot antenna array. The center frequency and bandwidth of the antenna were 6 and 9.2 GHz, respectively. The GMP train having the pulse width of 160 ps was generated by the 65 nm CMOS logic circuit with a core area of 0.0017 mm2 and was emitted by the 4 × 4 planar slot antenna array. The fabricated planar 4 × 4 antenna array with the matching layer could resolve the two separate 5 × 5 × 5 mm3 breast tumor phantoms, which were located at the depth of 22 mm with the spacing of 8 mm.

Characteristics of metal–oxide–semiconductor field-effect transistors with a functional gate using trap charging for ultralow power operation

A functional gate metal–oxide–semiconductor field-effect transistor that enables self-adjustment of threshold voltage (Vth) was developed for the ultralow power operation. The operating principle enables the on-current to be increased without increasing the off-current. Prototype devices were fabricated with complementary metal–oxide–semiconductor (CMOS) fabrication technology using a silicon-on-insulator substrate, and the fundamental device characteristics necessary for ultralow power operation were demonstrated with an emphasis on the device reliability. A negative Vth shift was caused by electron ejection from the poly-Si charge trap layer, and a positive Vth shift was caused by electron injection from the top gate electrode. A fabricated device endured 105 electron ejection-and-injection cycles when only a positive bias Vg was applied. Endurance characteristics of the fabricated devices showed that the number of cycles to oxide breakdown increased as the channel size decreased. The authors explained the SiO2 breakdown mechanism by using a percolation model. They consider that scaling down of the channel size and the thickness of the tunnel gate oxide will open the way to the development of CMOS logic applications for this device.

A Spin-Diode Logic Family

While most modern computing technologies utilize Si complementary metal-oxide-semiconductor (CMOS) transistors and the accompanying CMOS logic family, alternative devices and logic families exhibit significant performance advantages. Though heretofore impractical, diode logic allows for the execution of logic circuits that are faster, smaller, and dissipate less power than conventional architectures. In this paper, magnetoresistive semiconductor heterojunctions are used to produce the first complete logic family based solely on diodes. We utilize the diode magnetoresistance states to create a binary logic family based on high and low currents in which a full range of logic functions is executed. The diode is used as a switch by manipulating its magnetoresistance with current-carrying wires that generate magnetic fields. Using this device structure, we present basis logic elements and complex circuits consisting of as few as 10% of the devices required in their conventional CMOS counterparts. This diode logic family is therefore an intriguing potential replacement for CMOS technology as Si scaling reaches its inherent limits.

Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-k/Cu Back End on the Line Layers

We have confirmed the basic performance of a new logic intellectual property (IP) compatible (LIC) embedded dynamic random access memory (eDRAM) with cylinder capacitors in the low-k/Cu back end on the line (BEOL) layers. The LIC-eDRAM reduces the contact (CT) height, or essentially the RC delays due to the parasitic component to the contact. By circuit simulation, a 28-nm-node LIC-eDRAM with the reduced CT height controls the logic delay with Δτd < 5% to that of 28-nm-node standard complementary metal oxide semiconductor (CMOS) logics, enabling us ensure the logic IP compatibility. This was confirmed also by a 40-nm-node LIC-eDRAM test-chip fabricated. The 40-nm-node inverter delays in the test-chip were controlled actually within Δτd < 5%, referred to those of a pure-CMOS logic LSI. Meanwhile the retention time of the DRAM macro was in the range of milliseconds, which has no difference to that of a conventional eDRAM with a capacitor-on-bitline (COB) structure. The LIC-eDRAM is one type of BEOL memory on standard CMOS devices, and is sustainable for widening eDRAM applications combined with a variety of leading-edge CMOS logic IPs, especially beyond 28-nm-nodes.

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12MHz, a 4×4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4×4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4×4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors.

Supply-Voltage Scaling Close to the Fundamental Limit Under Process Variations in Nanometer Technologies

The fundamental limit on the minimum allowable supply voltage of a complementary metal-oxide-semiconductor (CMOS) logic gate for binary signal discrimination is Vdd, min ≅ 2(ln2)kT/q. With the theoretical analysis of our proposed circuit technique, we demonstrate an ultralow-voltage operation with two 1000-stage inverter chains fabricated in 130- and 65-nm technologies, which can work all the way down to a supply voltage of 50 and 60 mV (with output swings of 42 and 43 mV), respectively, and are close to the fundamental limit of logic operation. For the first time, we present a measured minimum dynamic-switching energy of 21.3 aJ/cycle. This is accomplished by modulating the effective β-ratio to balance the p-channel and n-channel MOS transistors in strength, enabling the operation of standard CMOS logic at ultralow voltages. We also discuss 41-stage ring oscillators, which clearly show the existence of different optimal β-ratios in different regions of operation in terms of performance and robustness under process variations.

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation

Magnetic random access memory (MRAM) has been considered as a promising memory technology because of its attractive properties such as non-volatility, fast access, zero standby leakage and high density. Although integrating MRAM with complementary metal-oxide-semiconductor (CMOS) logic may incur extra manufacturing cost because of the hybrid magnetic-CMOS fabrication process, it is feasible and cost-effective to fabricate MRAM and CMOS logic separately and then integrate them using 3D stacking. In this work, we first studied the MRAM properties and built an MRAM cache model in terms of performance, energy and area. Using this model, we evaluated the impact of stacking MRAM caches atop microprocessor cores and compared MRAM against its static random access memory (SRAM) and dynamic random access memory (DRAM) counterparts. Our simulation result shows that MRAM stacking can provide competitive instruction-per-cycle (IPC) performance with a large reduction in power consumption.