Logic Circuit Structure Research Articles

Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition

Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) logic in some specialized areas due to providing ultra-fast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools specialized for RSFQ logic are required due to the divergences in logic type, timing constraints, and circuit structure compared with CMOS logic. Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis. For the RSFQ logic, the sequential circuit synthesis is challenging, especially for non-linear sequential blocks with feedback loops. Thus, this paper presents a sequential circuit synthesis algorithm based on finite state machine (FSM) decomposition, which ensures design functionality, lowers costs, and improves the RSFQ circuit performance. Additionally, we present the synthesis processes of the feedback logic and the 2-bit counter to demonstrate how the proposed algorithm operates, and ISCAS89 benchmark circuits reveal our method’s ability to synthesize large-scale sequential circuits.

A 35 V–5 V monolithic integrated GaN-based DC–DC floating buck converter

The paper presents the development of a GaN DC–DC power converter with a pre-driver module and power device based on a monolithic integrated GaN E/D-mode metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) platform. The pre-driver module with direct coupled field effect transistor logic circuit structure has been monolithically integrated with a GaN power transistor on a Si-based AlGaN/GaN commercial epitaxial wafer. The MIS-HEMTs structure adopts an insulated gate dielectric layer to suppress the leakage current and increase gate voltage robustness. The GaN-based floating buck converter employs a 1 mH inductor and a 9 μF capacitor to achieve 35 V–5 V power conversion. As a result, the pre-driver module is capable of delivering a 10 V driving voltage. GaN monolithic integration of the pre-driver module and power device can reduce the system area in the DC–DC application, which allows for an integrated chip size of 1.8 mm2.

Compact all-optical decoder design for optical integrated circuits.

This paper constructs and discusses a 1×2 decoder based on two-dimensional photonic crystals. The designed decoder is a priority decoder with one main input and one enabled input. This logic circuit's structure is very simple and compact, and it employs a photonic crystal structure with dimensions of 11×11 rods built of GaAs. The calculation results reveal that the output power values for logical mode 1 are extremely close to the power of the light source, whereas the power is very low and close to zero in logical mode 0. As a result, the difference between logical values 0 and 1 in the output will be adequate, and the circuit's accuracy will be good. The finite difference-time domain (FDTD) approach is used for time computations and light propagation in waveguides.

Progress on Memristor-Based Analog Logic Operation

There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this need is increasing day by day. However, conventional design methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology cannot meet the performance requirements. The memristor, as a promising computing and memory integration device, offers a new research idea for conventional logic circuit structure and architecture innovation, given its non-volatility, scalability, low power consumption, fast switching speed, etc. This paper proposes a brief overview of the characteristics and current status of memristor-based logic circuits and analyzes their applications in numerical expression and memory. The benefits and drawbacks of various analog logic circuit structures are summarized and compared. In addition, some solution strategies for these issues are presented. Finally, this paper offers prospects for the applications of memristors in the logic implementation of large-scale memristor arrays, the novel structure of in-memory computing, and neural network computing.

Active loaded source-coupled logic: Applications and performance comparison

In this paper, we provide an extensive analysis of the newly introduced Active Loaded Source-Coupled Logic (ALSCL) family, which is a single-ended type of logic gate family with source-coupled circuit working principles. The proposed source-coupled logic family has analog-friendly behavior similar to previous source-coupled logic circuits, however, the proposed circuit structure has a simpler design methodology with high noise margins and robust characteristics to the device sizing, process variations, and temperature. Circuit design principles of the proposed ALSCL circuits are described, and performance analysis of various implementations is evaluated. The proposed logic circuit structure performance is tested using 0.18 µm technology with extensive simulations. The proposed logic family has simpler routing requirements compared to classical source-coupled circuits. The proposed circuit structure is functional without fine adjustment of the device sizing and the performance can be tuned by the bias current of the circuits, providing a wide range of performance characteristics with the trade-off for power consumption.

Cost effective Tanh activation function circuits based on fast piecewise linear logic

In this paper, an approximate 16-bit non-linear Tanh function circuit design is proposed for activation function in neural networks and digital signal processing, which is based on piecewise linear calculation. By sacrificing acceptable accuracy in computation, the proposed logic circuit structure can furtherly improve the overall performance of the design, with marked reduction in delay, area and power consumption. Linear calculation segments with simple shift-and-add logic architectures are adopted for easy hardware implementation. Additionally, tailored bias tuning and approximate accumulator design make a fine balance between complexity and error distribution. The mean absolute error (MAE) of the entire design is 0.0049. Compared with other state-of-art works in 90 nm CMOS process, the area of the circuit is 582μm2, and the energy is 0.0996 mW/GHz at 0.71 GHz. Moreover, the area-delay product is reduced by over 79.7% and the energy-delay product is reduced by over 42.4%. In the evaluation of its suitability in large applications, the accurate Tanh circuit and the proposed Tanh circuit are adopted in two neural networks to classify the Fashion-MNIST data and emotional EEG data. When the model converges, the accuracies of the test set only differs with a maximum of 0.2% and 0.3%.

An optoelectronic device based on bacteriorhodopsin with modulated photocurrent waveform

Developing novel photoelectric devices by functional biophotoelectric materials, especially environmentally friendly and biocompatible natural biomaterials are of great significance in the emerging field of bioelectronics. Bacteriorhodopsin (bR) has attracted much attention because of its good stability and light response since it was found. The response signal of photoelectric devices employing proton pump function of bR often exists in differential form, however, the typical electronic unit prefer to obtain square-wave signals with controllable duty cycles, which is the basis of the logic circuit structure. In this paper, we report an optoelectronic device based on bR molecule with modulated photocurrent waveform, which is achieved to use external bias to increase the duration of photocurrent, so as to form photocurrent similar to square wave signal. This improvement will contribute to the application of such biological devices as logic units in the field of digital circuits and optical communication, and provide a new idea for the development of new optoelectronic molecular devices.

A Novel Proposal for All-Optical OR/AND Gate Using Nonlinear Photonic Crystal Ring Resonators

AbstractIn this paper, we aim to design an all-optical structure that can be employed as optical OR/AND logic gates. To do so, a nonlinear photonic crystal-based ring resonator will be designed whose resonant wavelength depends on the variation of optical intensity. Then, by adding some optical waveguides, the optical logic circuit structure will be obtained that can function as optical OR/AND logic gates. The maximum time delay for the proposed structure is about 1.5 ps. Total footprint of the proposed structure is about 372 mm2. The proposed structure has lower time delay, lower footprint and lower optical input power compared with previously proposed structures.

Molecular Full Adder Based on DNA Strand Displacement

A new method, namely DNA strand displacement (DSD), has recently emerged in the field of biocomputing. DSD uses the toehold domain as a starting point to cover the strand in the migration domain. In this study, a molecular full adder composed of a molecular basic logic gate, including AND and XOR logic gates, is constructed based on strand displacement and Visual DSD. We used Visual DSD to simulate the molecular full adder. The experimental results show that the molecular full adder can be used for addition logic calculation. In addition, it can realize multi-bit addition logic calculation through a multi-stage cascade reaction. The simulation results verified the efficiency and reliability of our multi-bit molecular full adder, and our method can be used to design complex DNA integrated circuits. This research will lay the foundation for the formation of more complex molecular logic circuit structures and functions, as well as provide new coding ideas for various biocomputing related fields.

Fine-Grained Defect Diagnosis for CMOL FPGA Circuits

Nanotechnology is an important technological alternative to overcome the limitations of complementary metal-oxide-semiconductor (CMOS) technology. Various circuit implementation methods based on nanotechnology have been proposed, and their most important characteristics are a high defect ratio and defect tolerance through circuit reconfiguration. CMOS-nanowire-MOLecular (CMOL) field-programmable gate array (FPGA) circuits are advanced logic circuit structures that combine the advantages of CMOS and nanotechnology. However, researches on defect diagnosis methods for the reconfiguration of CMOL FPGA circuits are barely conducted. In this paper, efficient circuit configuration methods for defect diagnosis of the CMOL FPGA circuits are proposed to address the problem. Also, diagnosis algorithms for both stuck-at open and stuck-at close defects are introduced. Experimental results show that with the proposed methods, diagnosis is possible for CMOL fabrics with up to 20% stuck-at open defects and 0.02% or more stuck-at close defects.

Design Arithmetic Circuits Using Quaternary Logic

Arithmetic circuits play a really important role in each all-purpose and application specific procedure circuits. Multiple Valued Logic (MVL) provides the key good thing about the next density per computer circuit space compared to ancient 2 valued binary logic. Quaternary (Four-valued) logic conjointly offers the good thing about simple interfacing to binary logic as a result of base four (=22) permits for the utilization of straight forward encoding/decoding circuits. The purposeful completeness is well-tried with a collection of basic quaternary cells. The library of cells supported the Supplementary Symmetrical Logic Circuit Structure (SUSLOC) square measure designed, simulated, and accustomed build many quaternary fixed-point arithmetic circuits like adders, multipliers. These SUSLOC circuit cells square measure valid mistreatment SPICE models and also the arithmetic architectures square measure valid mistreatment System Verilog models for purposeful correctness. Quaternary (radix-4) twin quantity secret writing principles square measure applied to optimize power and performance of adder circuits mistreatment common place cmos gate technologies. Index Terms: Multiple-valued logic, Quaternarylogic, Modulo-n addition , subtraction and multiplication, Galois.addition and multiplication.

Design Modulo-4 and Galois Field Adder, Subtractor and Multiplier Using Quaternary Logic

Arithmetic circuits play a very necessary role in every general and application specific procedure circuits. Multiple Valued Logic (MVL)provides the key smart factor concerning future density per circuit area compared to ancient two valued binary logic. Quaternary (Four-valued) logic jointly offers the nice factor concerning easy interfacing to binary logic as a results of base four (=22) permits for the use of easy encoding/decoding circuits. The purposeful completeness is proved with a set of basic quaternary cells. The library of cells supported the Supplementary Symmetrical Logic Circuit Structure (SUSLOC) unit of measurement designed, simulated, and accustomed build several quaternary fixed-point arithmetic circuits like adders, multipliers. These SUSLOC circuit cells unit of measurement valid practice SPICE models and additionally the arithmetic architectures unit of measurement valid practice System Verilog models for purposeful correctness. Quaternary (radix-4) twin amount secret writing principles unit of measurement applied to optimize power and performance of adder circuits practice common place cmos gate technologies.

Novel Test Generation Algorithm for Combination Circuits

It has been known for many years that combinational circuits have a Complete Test Set (CTS) which is capable of detecting all single and multiple faults. In this paper, we attempt to find CTS systematically. Our algorithm finds a test set which detects all single and multiple stuck-at faults in combinational circuits. This test set is obtained without probing internal nodes, using fault simulation or fault enumeration. It is shown that the test set is independent of logic circuit structure and dependent to the mapping function, number of inputs, outputs, and fanout stems. An upper-bound and lower-bound figures for the number of test vectors required to obtain 100% fault coverage are provided. This number is a small fraction of the entire solution space. A number of recommendations are made to improve the testability of a logic circuit.

NOVEL TEST GENERATION ALGORITHM FOR COMBINATION CIRCUITS

It has been known for many years that combinational circuits have a Complete Test Set (CTS) which is capable of detecting all single and multiple faults. In this paper, we attempt to find CTS systematically. Our algorithm finds a test set which detects all single and multiple stuck-at faults in combinational circuits. This test set is obtained without probing internal nodes, using fault simulation or fault enumeration. It is shown that the test set is independent of logic circuit structure and dependent to the mapping function, number of inputs, outputs, and fanout stems. An upper-bound and lower-bound figures for the number of test vectors required to obtain 100% fault coverage are provided. This number is a small fraction of the entire solution space. A number of recommendations are made to improve the testability of a logic circuit.

Energy-recovery flip-flop design using improved adiabatic pseudo-domino logic structure

Adiabatic or energy-recovery logic families have been reported in the literature for low-power applications (A.G. Dickinson, J.S. Denker, Adiabatic dynamic logic, IEEE Journal of Solid-State Circuits 30(3) (1995) 311–315; D. Maksimovic, V.G. Oklobdzija, Clocked CMOS adiabatic logic with single AC power supply, in: Proceedings of the Twenty-First European Solid-State Circuits Conference, 1995, pp. 370–373; Y. Moon, D.K. Jeong, An efficient charge recovery logic circuit, IEEE Journal of Solid-State Circuits 31(4) (1996) 514–522; W.Y. Wang, K.T. Lau, Adiabatic pseudo-domino logic, Electronics Letters 31(23) (1995) 1982–1983; K.T. Lau, F. Liu, Improved adiabatic pseudo-domino logic family, Electronics Letters 33(25) (1997) 2113–2114; K.T. Lau, F. Liu, Four-phase improved adiabatic pseudo-domino logic, Electronics Letters 34(4) (1998) 343–344; S.M. Yoo, S.M. Kang, A bootstrapped NMOS charge recovery logic, in: Proceedings of the IEEE Great Lakes Symposium on VLSI, 1998, pp. 30–33). These designs have concentrated on combinational logic. In this article, SR flip-flop and JK flip-flop designs based on the Improved Adiabatic Pseudo-Domino Logic (IAPDL) circuit structure and the auxiliary clocking system of the IAPDL-4 φ (four-phase IAPDL) are presented. Besides the reduced transistor count, HSPICE simulations performed indicate significant improvement in terms of power consumption over CMOS transmission gate-based flip-flops.

VLSI-oriented design method of asynchronous sequential circuits based on one-hot code and two-transistor and logic

This paper proposes a new method of synthesis for a CMOS LSI-oriented asynchronous sequential circuit with the two-transistor AND logic structure, using the one-hot code for the internal state assignment. The assignment of the state by the one-hot code is executed uniquely, independently of the properties of the state-transition table. The CPU time for state assignment, which has been a problem, can be ignored. The critical race-free property, which is then a problem, is solved by a 4-FET set/reset flip-flop which stores the state variable and the drive circuit for the flip flop, not the internal code assignment. The set and the reset driving circuits have the AND logic circuit structure, where two transistors are placed (with the state variable and the external input as the gate inputs) on each conduction path. The synthesized circuit is hazard-free. It realizes a pseudo-CMOS operation without static power consumption. Comparing the method proposed in this paper with other methods of synthesis, it is compact and especially suited to the large-size asynchronous sequential machine (with 40 or more cells in the row-column product of the state transition table).

New dynamic logic and memory circuit structures for BICMOS technologies

The basic structure is based on merging three devices in an area of a single MOS transistor. It uses an MOS capacitor and bipolar and JFET transistors for storage, writing, and sensing, respectively. These circuit structures have significantly smaller area and faster speed of operation compared to the conventional dynamic logic and memory circuits. In dynamic serial memory, the area of the circuit structure is approximately 35% that of the conventional circuit. The circuit structures also do not suffer from the common problem of charge redistribution.

A placement method based on logic circuit structure information

AbstractLogic circuits for VLSI have become more and more attractive. This paper presents a new placement method reflecting such logic circuit structural features as signal flow direction and logically repeated structure in the chip layout. The placement steps are as follows. The logic synthesis system synthesizes multilevel Boolean expressions for the function block from their high‐level functional specifications and outputs a relative layout for these Boolean expressions. The Boolean expressions are then mapped into physical gates. Finally, the layout system determines the position of physical gates using the relative layout and the mapping information.