Simulation Of Logic Circuits Research Articles

Study of FIT Dedicated Computer with Dataflow Architecture for High Performance 2-D Magneto-Static Field Simulation

An approach to dedicated computers is discussed in this study as a possibility for portable, low-cost, and low-power consumption high-performance computing technologies. Particularly, dataflow architecture dedicated computer of the finite integration technique (FIT) for 2D magnetostatic field simulation is considered for use in industrial applications. The dataflow architecture circuit of the BiCG-Stab matrix solver of the FIT matrix calculation is designed by the very high-speed integrated circuit hardware description language (VHDL). The operation of the dedicated computer's designed circuit is considered by VHDL logic circuit simulation.

Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology

Abstract Bit manipulation plays a significant role in high-speed digital signal processing (DSP) and data computing systems, and shift and rotation operations are crucial functions in it. In general, barrel shifters are used to perform these operations effectively. Nano magnetic logic circuits are among the promising beyond-CMOS alternative technologies for the design of high-speed circuits. Most of the existing circuits that have been developed using nano magnets are combinational circuits. In this work, a barrel shifter is implemented and realised using in-plane nano magnetic logic. The proposed design is the first of its kind nano magnetic logic circuit. The nano magnetic logic circuit implementation, layout generation, simulation, and validation were performed using the ToPoliNano and ModelSim tools. The logical equivalent design was synthesised and evaluated using the Synopsys Design Compiler tool. The proposed barrel shifter was realised using majority logic has 1769037 nano magnets with a boxing area of 481 × 13104 µm2 and 3276 clock zones after optimisation with the Barycenter algorithm. The proposed barrel shifter realised using Boolean logic has 315276 nano magnets with a boxing area of 265 × 5028 µm2 and 1257 clock zones after optimisation with the Barycenter algorithm. The proposed design results demonstrate that complex systems can be developed using nano magnetic logic by combining combinational and sequential circuits.

A design of EEGNet‐based inference processor for pattern recognition of EEG using FPGA

AbstractIn recent years, brain‐machine interface (BMI) is attracting attention. BMI is a technology that enables machine operation using biological signals such as EEG. For further advancement of BMI technology, there is a need for advanced BMI devices. Therefore, the purpose of this study is development of BMI hardware specialized for handling EEG as an interface for human adaptive mechatronics (HAM) that know human's state and operate according to the state. As one of the examinations, we are constructing a pattern recognition processor for EEG in real time on Field Programmable Gate Array (FPGA), which is an LSI that can reconfigure the processor. This paper reports on the designed EEGNet processor and the result of logic circuit simulation and implementation.

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory.

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).

Orthodox Theory Monte-Carlo Simulation of Single-Electron Logic Circuits

In the past decades MOS based digital integrated logic circuits have undergone a successful process of miniaturisation eventually leading to dimensions of a few nanometres. With the dimensions in the range of a few atomic radii the end of conventional MOS technology is approaching. Amongst the prospective candidates for sub 10nm logic are integrated logic circuits based on single-electron devices. In our contribution we present the use of MOSES (Monte-Carlo Single-Electronics Simulator) as a method for simulation of complementary single-electron logic circuits based on the orthodox theory. Simulations of single-electron devices including a single-electron box, a single-electron transistor and a complementary single-electron inverter were carried out. Their characteristics were evaluated at different temperatures and compared to measurement results obtained at other institutions. The potential for room-temperature operation was also assessed.

NMLSim: a Nanomagnetic Logic (NML) circuit designer and simulation tool

Nanomagnetic Logic (NML) is a new technology based on nanomagnets. Logic operations are performed at room temperature through dipolar magnetostatic interactions. The low switching energies involved in the operation of NML circuits in addition to the possibility of higher integration density are remarkable advantages of this technology over CMOS-based systems. Although intense work has been done on the physical behavior of the NML systems, simulation tools for the study of large and complex NML architectures are lacking. In this paper, we present a fast and robust computational tool that allows the design and simulation of complex NML circuits. We developed a new fast simulation engine based on single-domain approximation able to capture both the static and dynamic behaviors of the system. The tool simulates the clock, the magnet influence in between neighbors and the thermal effect on the circuit. Initial results show a good agreement with experimental and micromagnetic simulations works. To the best of our knowledge, this is the first open-source NML simulator available and serves as a complete tool to design and evaluate complex NML circuits.

A Logic Circuit Simulation for Finding Identical or Redundant Files using Counter and Register

Computers and internet have become globally used nowadays and also part of the important facilities that could support information exchanges and cloud computing. People deals with texts, images, and videos processing, reaches out the specific goal of their works. It happens that due to much information and procedures, people will have many redundant files such as images or videos in their host computers or terminals, or maybe for some specific reasons people need to find data from big servers that surely have many files with same type and property because people accidentally put them there without knowing others also probably put the same ones. Using the basic concept of sequential logic circuit and electronic workbench 5.12 software, a logic circuit simulation consists of counter and register could be designed to show logically how to a computer or digital machine would interact to find redundant files, images or videos, or same files from many identical data from a server. The methods being used are study literature, analysis, design, and simulation. The output shows an expected result, a logic circuit simulation that could be applied on digital devices for finding identical or redundant files, or other related important process.

A Logic Circuit Simulation for Choosing a Group or a Question using Register and Encoder

Besides learning and working individually, normally people also interact in a group. A teacher or manager will divide and put several persons in groups, and mostly the group arrangement will be organized according to some classifications. This is quite different when people are dealing with a specific game or quiz. The participants will be asked to choose their own group or question in random order. Using the basic concept of digital system and electronic workbench 5.12 software, a logic circuit could be designed to build a circuit simulation consists of register and encoder which can be used to choose a group or a question randomly. The methods being used are study literature, analysis, design, and simulation. The result shows a desired output, a logic circuit for choosing a group or a question can be built using register and encoder logic components. Once a group or a question has been chosen, it cannot be chosen and displayed again.

Ternary Electronic Logic Systems Automation: A Novel Study Based on VHDL Language - First Part: Ternary Logic Gates

In this scientific paper, a software library for Ternary logic gates will be built based on VHDL language to be used in the implementation of combinational Ternary logic circuits. The VHDL language had been designed to be used to automate and design Binary electronic logic systems. Therefore, several problems have been arised in adapting the VHDL language to be used with Ternary electronic logic systems. However, these problems have been solved and the result were encouragement to continue the study with the other Ternary components, so that a complete software library based on VHDL language for different Ternary components will be used as a tool in the design and simulation of Ternary electronic logic circuits and systems. 
 Keywords: Ternary logic, Ternary logic gates, VHDL language.

Simulation of FeFET-Based Basic Logic Circuits and Current Sensing Amplifier

The usage of ferroelectric-gate field effect transistors (FeFET) in digital circuits has typically been its applications in memory. The use of FeFET to implement logic circuits is neither completely understood nor extensively studied. This paper presents simulations of electrical properties of a single FeFET and the resulting behavioral characterizations of FeFET-based basic logic circuits in a commercially available TCAD environment. The all-FeFET current mirror, CMOS inverter, 2-input-NAND and 2-input-NOR logic circuits show almost the same electrical characteristics as standard MOSFET ones, except for the negligible clockwise hysteresis under the condition of low voltage supply. Moreover, the all-FeFET current mode sensitive amplifier whose component units were all-FeFET common-source amplifier, current mirror and differential amplification, also works reasonably.

Visualization Engineering Simulation Based on HTML5 and Cloud Computing

Visualization Engineering Simulation Based on HTML5 and Cloud Computing is the first product using web technology in the development of simulation.This hardware simulation platform is a visualization simulation platform like Simulink, which is based on the browser, and provides a integrated environment with dynamic systems modeling, simulation and comprehensive analysis. The platform adopted HTML5 system, realize the cross-platform simulation.By calling the HTML5 standard Canvas 2D Graphics and other new technology, developers can visually control elements and logic circuit simulation tests, and it truly realize the span of PC, Android, BB10 and other operating system platforms for the work.Simulation of the platform carry out in the clouds,and the simulation process lower the requirements over equipment, therefore the requirements on the hardware in developing becomes transparency.Long term, the platform will be the focus shifted to engineering simulation development of Internet air.

Study on Fault Detection and PCB Picture-Location Method of Logic Circuit

The main content of logic circuit fault detection includes describing circuit to be diagnosed, determining fault and circuit initial information, generating circuit location test set. In this study, LASAR is used to carry out the logic circuit simulation so as to create such documents as fault dictionary, node truth value table, etc. for the preparation of fault detection. Due to the limitation of circuit observability and testing vectors, the diagnosis program can not accurately locate the fault just once in the process of diagnosis because the circuit is complex and users are not quite familiarity with the circuit. Therefore, the new circuit-fault-detection technology incorporates techniques of PCB picture-location so that the users can locate the fault quickly and accurately.

Device and SPICE modeling of RRAM devices

We report the development of physics based models for resistive random-access memory (RRAM) devices. The models are based on a generalized memristive system framework and can explain the dynamic resistive switching phenomena observed in a broad range of devices. Furthermore, by constructing a simple subcircuit, we can incorporate the device models into standard circuit simulators such as SPICE. The SPICE models can accurately capture the dynamic effects of the RRAM devices such as the apparent threshold effect, the voltage dependence of the switching time, and multi-level effects under complex circuit conditions. The device and SPICE models can also be readily expanded to include additional effects related to internal state changes, and will be valuable to help in the design and simulation of memory and logic circuits based on resistive switching devices.

Modeling and simulation of combinational CMOS logic circuits by ANFIS

In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training. Influence of the structure of the proposed ANFIS model on accuracy and network performance has been analyzed through some combinational circuits. For the comparison of the ANFIS simulation results, we have simulated the circuits in HSPICE environment with 0.35μm process nominal parameters. The comparison between ANFIS, HSPICE, and real hardware shows the feasibility and accuracy of the proposed ANFIS modeling procedure. The results show the proposed ANFIS simulation has much higher speed and accuracy in comparison with HSPICE simulation and it can be simply used in software tools for designing and simulation of complex CMOS logic circuits.

Generic and Accurate Whitebox Behavioral Model for Fast Simulation of Analog Effects in Nanometer CMOS Digital Logic Circuits

Digital CMOS circuits are praised because of their noise immunity. However, lowering power supply voltages and shrinking device sizes, in combination with the rising electromagnetic pollution, have made this statement no longer true. An accurate behavioral model is presented for the analog simulation of digital logic circuits. The model building is automated and scalable in the sense that it allows a tradeoff between model-building speed and accuracy. The proposed model is validated on a seven-stage CMOS ring oscillator and a 112-transistor 4-bit adder, excellent test cases to demonstrate the accuracy. The RMS error remains below 5% in case of electromagnetic interference, and below 2% in all other cases, while achieving speed-ups up to 400times.

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature

Single-electron transistors (SETs) provide current conduction characteristics comparable to CMOS technology and research shows that these devices can be used to develop logic circuits. It has been observed while building logic circuits that comprise only of SETs the voltage at the gate input had to be much higher than the power supply for the SET to have acceptable switching characteristics. This limitation in the gate and power supply voltages makes it practically inappropriate to build circuits. In this paper, we propose a hybrid architecture to overcome this limitation by combining conventional MOS devices with SETs. Three different types of hybrid circuits have been proposed and their characteristics have been studied using SPICE-based simulation tool which includes a SET-SPICE model.

Using digital logic circuit simulation to build demonstrations of IT concepts

This paper describes using an open source, freely available logic simulation package to build visualizations to teach IT concepts. The first visualization is of an XOR based, symmetric encryption/decryption process. While it is not the actual process used in modern encryption, it illustrates concepts that are used in encryption/decryption and are often used in IT, particularly in computer and Internet technology to protect files and secure transactions. While actual encryption would be over a much larger word size and use several passes in the encryption process, this tool clearly illustrates the basics of the process. A second visualization shows Hexadecimal numbers with their binary and decimal counterparts. These are important concepts in understanding how bit patterns can represent many different things within a computer. The flexibility of these visualizations is shown by a small circuit addition that can add ASCII characters to this display. Building these visualizations could be done with many different software tools; however, using a logic simulator for some visualizations has the advantages of being easy and also providing insight into the logic of the process that are being visualized.

A quasi-analytical SET model for few electron circuit simulation

A novel quasi-analytical model for single electron transistors (SETS) is proposed and validated by comparison with Monte-Carlo (MC) simulations in terms of drain current and transconductance. The new approach is based on the separate modeling of the tunneling and thermal components of the drain current, and verified over two decades of temperature. The model parameters are physical and an associated parameter extraction procedure is also reported. The model is shown to be accurate for SET logic circuit simulation in both static and dynamic regimes and is attractive for hybrid (SET-CMOS) circuit co-simulation.

Model partitioning and the performance of distributed timewarp simulation of logic circuits

Simulation of complex digital electronic systems requires powerful machines and algorithms. Distributed simulation could improve both the execution time and the availability of a large distributed memory for complex models. Model partitioning onto the available processors has a major impact on simulation efficiency. We report on how various partitioning algorithms affect timewarp-based distributed simulation of combinational and synchronous sequential logic circuits, and try to determine the relationship between circuit parameters (the number of gates, topological levels and the degree of activity in the circuit) and the structure of the partition having the fastest simulation on a heterogeneous network of Sun workstations.

Simulation of single-electron logic circuits

Using the Monte Carlo simulation which can handle the motion of each electron, the transient operation characteristic of a quasi-CMOS inverter circuit proposed by Tucker [1] was evaluated. It was found that: (1) the output voltage of the inverter circuit depends on the load capacitance, and (2) the propagation delay time can be as short as 10 ps if a tunnel junction with a capacitance of 1 aF is formed. In addition, by evaluating the standard deviation of the inverter output signal, the limit of operating temperature for the integrated circuit was analyzed quantitatively.