Abstract
A novel quasi-analytical model for single electron transistors (SETS) is proposed and validated by comparison with Monte-Carlo (MC) simulations in terms of drain current and transconductance. The new approach is based on the separate modeling of the tunneling and thermal components of the drain current, and verified over two decades of temperature. The model parameters are physical and an associated parameter extraction procedure is also reported. The model is shown to be accurate for SET logic circuit simulation in both static and dynamic regimes and is attractive for hybrid (SET-CMOS) circuit co-simulation.
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