Logic Arrays Research Articles

All-optical programmable array logic unit using semiconductor optical amplifier-based polarization switch

The demand for optical communication technology increases rapidly, and the frequency encoded data-based communication establishes an important place in optical communication technology because of the constancy and transparency of the frequency encoded data throughout the communication network. In this article, the authors have proposed a new method of developing an all-optical programmable array logic unit deploying semiconductor optical amplifier-based polarization switches with an attractive frequency-based data encoding technique. The authors have first developed some fundamental all-optical logic gates exploiting the polarization-based switching action of semiconductor optical amplifiers, and successively developed a method to design a programmable array logic unit using the fundamental logic arrays. This unit can be deployed to execute 16 different types of logic operations only by changing the frequency of the control signals. The simulation-aided result increases the practicability of the proposed circuit design.

Discrimination method of low-current grounding fault of primary and secondary integrated equipment under three-phase asymmetric harmonic power flow calculation

In order to realize the accurate judgment of the ground fault and improve the fault discrimination effect, this paper proposes a low-current ground fault discrimination method for the primary and secondary fusion complete sets of equipment under the calculation of three-phase asymmetric harmonic power flow. The three-phase asymmetric harmonic power flow calculation is carried out, the ground fault line selection model is constructed according to the calculation results, and the faulted line is obtained by the zero-sequence active component method and the zero-sequence reactive power component method; the wavelet packet transform method is used to extract the transient zero-sequence power direction, and use it as a line selection criterion to identify whether a ground fault occurs. The amplitude characteristic enhancement value of each section is obtained by calculation. According to the distribution characteristics of the zero-sequence current amplitude of the faulted feeder, the corresponding section is selected as the fault section, and the mutation logic array is used in the determined fault section to realize the low-current grounding fault judgment. The experimental results show that the method has high judgment accuracy in practical application, and the highest value is 98.5 %, which indicates that the method can accurately judge the fault line and determine whether ground fault occurs.

LSAB: Enhancing Spatio-temporal Efficiency of AoA Tracking Systems

Estimating the angle-of-arrival (AoA) of an RF source by using a large-sized antenna array is a classical topic in wireless systems. However, AoA tracking systems are not yet used for Internet of Things (IoT) in the real world due to their unaffordable cost. Many efforts, such as a time-sharing array, emulated array, and sparse array, were recently made to cut the cost. This work introduces a log-spiral antenna belt ( LSAB ), a new novel sparse “planar array” that could estimate the AoA of an IoT device in 3D space by using a few antennas connected to a single timeshare channel. Unlike the conventional arrays, LSAB deploys antennas on a log-spiral-shaped belt in a non-linear manner, following the theory of minimum resolution redundancy newly discovered in this work. One physical 8 × 8 uniform planar array (UPA) and four logical sparse arrays, including LSAB , were prototyped to validate the theory and evaluate the performance of sparse arrays. The extensive benchmark demonstrates that the performance of LSAB was comparable to that of a UPA, with similar degree of resolution; and LSAB could provide over 40% performance improvement than existing sparse arrays. We also prototyped a second LSAB adapted to an RFID system for localizing RFID tags at centimeter-level accuracy.

Simultaneous full set of three-input canonical logic units in a single nonlinear device for an all-optical programmable logic array

All-optical canonical logic units-based programmable logic array (CLUs-PLA) is an important combinational logic device owing to its flexibility and user-defined feature. However, the limited number of three-input CLUs generated in a single nonlinear device hinders their practical application. In this study, we overcome this limitation and experimentally demonstrate the simultaneous generation of a full set of three-input CLUs in only one nonlinear device. By performing bidirectional four-wave mixing (FWM) and wavelength spacing optimization, the all-optical three-input PLA with a full set of CLUs enables arbitrary functions. We experimentally demonstrate the implementation of a series of combinational logic functions including, user-defined logic functions, full adder, and full subtractor, exhibiting error-free performances for all logic operations at 40 Gb/s. The scheme can reduce the number of nonlinear devices in CLUs-PLA, which simplifies the computing system and reduces power consumption. Therefore, the scheme has great potential for future high-speed optical computing systems.

Cost-effective Programmable Logic Arrays Using Multilayer Structures of Decoders in QCA Framework

The emerging nanotechnology paradigm, Quantum Dot Cellular Automata (QCA) in particular, is gaining a wide recognition due to its high speed, nano feature size and considerably low power consumption. The QCA architecture not only provide potential alternative for Complementary Metal Oxide Semiconductor (CMOS) circuits but its multilayer topology facilitates an added benefit of cost efficacy and immunity towards random interference. Moreover, design of programmable logic devices in QCA is vital to promote the multi-utility and resiliency of the computing circuits. This paper presents the multilayer designs of 2×4 and 3×8 decoder circuits in QCA framework with 55.1% and 51.17% better cost efficiency respectively, over the earlier reported designs. The presented 3×8 decoder circuit is further utilized to implement Programmable Logic Array (PLA) to realize Boolean functions of adder and subtractor. The presented circuits are cost effective and showcase the significance of programmable devices in nano-computing.

Application of Laser Scanning Technology in Digital Method

In order to improve the efficiency and accuracy of retrieval and mining of highway operation management information, a digital method research and application method based on laser scanning technology is proposed. Combined with the data storage and backup requirements of highway toll collection system, such as large amount of information, high reliability, easy management, and easy management, a complete design scheme of optical storage backup chip based on programmable logic array FPAG technology is proposed. The function, design, and simulation implementation of the write strategy subsystem and the laser power automatic control subsystem of the optical storage backup chip system are emphatically introduced. Through a lot of simulation tests, the scheme is reasonable and feasible, and its performance is stable and reliable.

Kāśī Kṣetra, Kāśī Maṇḍala: Digitally Mapping Evolving Interpretations of an Idealized Sacred City

This article employs digital mapping to better understand historical and contemporary interpretations of pilgrimage routes in Vārāṇasī, North India. Focusing on visitation circuits linking the Aṣṭabhairava (Eight Bhairavas), it compares digital maps of these circuits to descriptions in the fourteenth-century Kāśī Khaṇḍa, nineteenth- and twentieth-century maps, and contemporary listings and pilgrim activity. Mapping and comparing these variants illuminate ways in which sacred geographies are conceived of and interacted with, as well as the various authorities, explanations, and justifications used to make sense of complex systems in sacred spaces. This study does not support theories of the “degradation” of a previously more uniform or ideal sacred landscape, nor explanatory models which suggest that more contemporary routes are the result of historical waves of development. Rather, the routes mapped suggest that an array of context-contingent resources and logics are selected and combined based upon a particular agent’s immediate circumstance in order to determine appropriate ritual action. Instead of describing an historical arc or uncovering an obscured tension between authorities, this study identifies the toolkit with which the sacred territory of Vārāṇasī is remade and reinterpreted, over and again.

THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell&#x2013;along with the symmetry of the mask- and field-programmable gate array logic cells&#x2013;made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric.

Efficient 3D AlexNet Architecture for Object Recognition Using Syntactic Patterns from Medical Images.

In computer vision and medical image processing, object recognition is the primary concern today. Humans require only a few milliseconds for object recognition and visual stimulation. This led to the development of a computer-specific pattern recognition method in this study for identifying objects in medical images such as brain tumors. Initially, an adaptive median filter is used to remove the noise from MRI images. Thereafter, the contrast image enhancement technique is used to improve the quality of the image. To evaluate the wireframe model, the cellular logic array processing (CLAP)-based algorithm is then applied to images. The basic patterns of three-dimensional (3D) images are then identified from the input image by scanning the whole image. The frequency of these patterns is also used for object classification. A deep neural network is then utilized for the classification of brain tumor. In the proposed model, the syntactic pattern recognition technique is used to find the feature vector and 3D AlexNet is used for brain tumor classification. To evaluate the performance of the proposed work, three benchmark brain tumor datasets are used, i.e., Figshare, Brain MRI Kaggle, and Medical MRI datasets and BraTS 2019 dataset. The comparative analyses reveal that the proposed brain tumor classification model achieves significantly better performance than the existing models.

Humanities, Science, and Technology: The Nexus

Science and technology are complex terms as it involves laws, logical array of concepts, and series of practical experiments when compared to literature, which is an art form abounding in expressions. In science and technology, there are only two opinions: something could be only right or wrong. In literature, there are multitudes of opinions since it is viewed with different prisms. Moreover, there is no right or wrong in the humanities. Science concepts could only be understood by the field experts. However literature grants everyone the access to comprehend. When a research article elaborates on how technology would assist in forging a sustainable environment, the readers from non-technical background would find the concepts obscure because of the technical terms, laws, theories, and empirical results. Humanities address lifestyle, culture, philosophy, psychology to science, and technology. When technology infused concepts are furnished with literary narratives, the readers could effortlessly decipher. This style of writing marked its beginning when Rachel Carson published Silent Spring. The work addressed the adverse effect of using pesticides, inculcates environment friendly thoughts and insights, and stresses the need in educating the people on malign effects of pesticides. Even before that, writers like Henry David Thoreau and Ralph Waldo Emerson shaped their works artistically whilst insisting the readers to aim for a sustainable and harmonious living space. The primary objective of the paper is to unveil how literary chef d'oeuvre educates the readers on sustainable living through literary narrations and the role of humanities in promoting science and technology.

Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions

FPGAs can provide application-specific acceleration for computationally demanding tasks. However, they are rarely considered general-purpose platforms due to low productivity of software development and long reconfiguration time. These problems can be mitigated by implementing a coarser overlay atop the FPGA fabric. Combining this approach with partial reconfiguration allows for the modification of individual processing elements (PEs) of the virtual architecture without altering the rest of the system. Module relocation can be used to share implementation details between functionally equivalent PEs that use identical sets of resources, thus eliminating redundant placement and routing runs. Proper floorplanning is crucial for virtual Coarse-Grained Reconfigurable Architectures (CGRAs) with relocatable PEs considering their tendency to use nearest-neighbor connection patterns. It requires solving two problems—finding identical regions in the FPGA fabric and assigning individual partitions to certain locations. This article presents minor improvements of a state-of-the-art solution for the first and proposes a novel technique for solving the other. The proposed automated floorplanner uses modified breadth-first search with direction-based penalties to create initial floorplan consistent with geometry of logical array, then improves the result with 2-opt local optimization. Compared to simulated annealing solutions, the proposed approach allows for the reduction in the floorplanning time by two to three orders of magnitude without compromising the quality of the results.

Between the law and the actual situation: Failure as property formation in French colonial Indochina

This article complements and complicates Bhandar’s discussion of ‘racial regimes of ownership’ (2018) by examining the relational co-constitution of notions of racial and property formations in the ‘non-settler’ colonial context of Cambodia. Working through the record of intra-colonial correspondence relating to the control of non-white but also non-Khmer property interests in Cambodia, this article documents racialization’s powerful disruptive impact on liberal property formation. Colonial failure as property formation indexes, first, how the racialized categories of ethnic difference that underpinned the rationalities of French colonial rule simultaneously undermined French colonial programs to alienate land. Second, it positions the failure to reconcile a confusing array of property laws and logics as integral to maintaining paternalistic colonial (and post-colonial) authority to sort racialized populations via the privilege of property. Through the lens of French attempts to control property claims, we show how the French colonial property regime, supposedly based on universal liberal norms, was in fact also deeply racialized, requiring it to be managed in a highly localized manner, in accordance with each territory’s existing set of ethnic property relations—or the practical racial hierarchy of colonialism would unravel.

Study, implementation and testing of radiation tolerant design for testability solutions for CMS OT FE ASICs

The MPA and SSA development is approaching the production phase with an approximate volume of more than 200k ASICs, corresponding to 1200 wafers. The limited manufacturing yield requires testing strategies able to identify defective units and guarantee the correct functionality of the tracker modules. This contribution presents innovative methods to replace the currently used functional tests for the digital part of the ASICs, showing limited testing accuracy and long testing time. The proposed solution exploits the concept of structural test and new testing algorithms such as Automatic Test Pattern Generation (ATPG) for general digital logic and March for memory elements. Design for Testability (DFT) hardware is integrated on chip to test SRAM memories, peripheral logic and MPA pixel array, providing internal control and observation points for the implementation of the those algorithms. Particular attention is given to power increase, timing and placement impact as well as radiation tolerance of the introduced circuitry, which must be fully transparent during the normal operation of the chip. A faster and more accurate testing approach is presented, from design methodology to implementation choices and silicon results, for a reliable and cost effective testing procedure.

Reconfiguration algorithms for synchronous communication on switch based degradable arrays

Synchronous communication is one of the most important issues in high performance architectures for large scale of parallel computing, such as matrix computing, image processing, etc. Mesh-connected processor array is characteristic of synchronous communication due to the same length of the interconnects between the neighboring processing elements (PEs) in rows/columns. But long interconnects caused by faulty PEs clearly impact the synchronous communication between the adjacent rows/columns. If long interconnects exist between two adjacent rows, we say that a synchronous communication delay is caused. This paper contributes algorithms to construct logical arrays with synchronous communication in a given host array. Specifically, an algorithm for synchronous communication array (ASCA) is firstly presented, to construct a maximum logical array with synchronous communication. When all of the long interconnects are independent each other, the proposed algorithm is proved to be optimal. After that, two heuristic algorithms are also proposed, to construct a logical array with given size, by integrating the proposed ASCA and two exclusion schemes. The proposed two exclusion schemes are based on strategies of divide-and-conquer and the longest logical column first, respectively. In addition, the lower bound of synchronous communication delay for a logical array is calculated by an algorithm also developed in this paper, in order to evaluate the synchronous performance of reconfiguration algorithms. Simulation results show that, the proposed two heuristic algorithms have their own advantages for different cases. The synchronous communication delay of the logical arrays is significantly reduced, and it is very close to the lower bound for the cases of small fault density and larger exclusion rate. For 32 × 32 physical arrays with exclusion rates that are larger than 15%, the synchronous communication delay of logical array is reduced from 11.09 to 6.97, which is more closer to the lower bound 4.43, for different fault densities on average.

DTOF Image LiDAR With Stray Light Suppression and Equivalent Sampling Technology

This paper presents direct time-of-flight image LiDAR to realize a reliable autopilot system, which consists of hardware architecture and processing algorithm based on field programmable logic array (FPGA). The processing algorithm consists of multi-channel time-to-digital converters (TDCs), equivalent sampling technology consisting of equivalent sampling circuit (ESC) and amplitude fitting algorithm (AFA), correlation slope fitting algorithm (CSFA), and stray light suppression algorithm (SLSA). The TDCs are used to measure the flight time. The ESC is used to record waveforms based on time discrimination circuits, dynamic threshold adjustment circuits, and TDCs. The AFA is used to achieve the amplitude of the echo signal whether it is saturated or not. The CSFA based on the Gauss function is used to eliminate walk error, which does not need to calibrate the compensation coefficient in advance. And the stary light suppression algorithm based on laser pulse signal modulation technology is used to suppress the interference of background light and interference within different LiDAR systems. The LiDAR system can achieve 100 m measurement range with the laser peak power of 120 W. A measurement precision of ~+/−15 mm was achieved with non-cooperative targets when the measurement range was less than 10m. And the measured relative precision was less than 1% for a distance up to 100 m with a 100-klux direct sunlight.

A new design for programmable logic array based on QCA-based nanotechnology

Dissipation in the complementary metal-oxide-semiconductor circuit size range has become a challenge for designers seeking to create a circuit with low power consumption and significantly reduced size. As a result, there is a need for an alternative technology that may provide revolutionary results. The quantum-dot cellular automaton is now widely regarded as a viable alternative to complementary metal-oxide-semiconductor technology. This paper demonstrates a new circuit for constructing a quantum-dot cellular automaton-based programmable logic array. The programmable logic array is a promising, standard, and fully programmable architecture that can use redundancy to make circuits with nanoscale feature sizes more practical. The comparisons based on cell number, size, and clock phases were made between the proposed circuit and previous ones using the QCADesigner. These comparisons verified the efficiency of the proposed design. The suggested programmable logic array circuit consists of 26 cells and occupies 0.04 µm2. In addition, the quantum cost of this circuit is 2.08, and the area delay is 0.08.

Оптимізація схеми автомата Мілі в базисі FPGA

Introduction. The ubiquitous penetration of digital systems into all spheres of human activity has made obvious the desire to reduce hardware costs. If for the implementation of combinational circuits there are standard solutions used in various CAD systems, then for many types of accumulating blocks, which include control devices (CU), there are no standard library solutions. CU circuits, which are a sequential circuit, must be designed first each time because, as a rule, these circuits differ in an irregular structure and a complex interconnection system. The characteristics of the control device have a significant impact on the quality of the digital system, and therefore the issue of designing a control device is a responsible process that, as a rule, requires solving the problem of reducing hardware costs. Methods for solving this problem depend on the features of both the architecture of the control device and the elemental basis. Purpose. The main goal of this work is to reduce hardware costs and power consumption of control devices of digital systems by taking into account features of an element base of the control device and rational organization of micro-command addressing. FPGA (field-programmable logic array) microcircuits, widely used for the implementation of modern digital systems, were chosen as an elementary basis. Methods. To evaluate the effectiveness of solving the problem, we used the methods of set theory, synthesis of automata, and software simulation using Xilinx Vivado CAD. Results. The paper proposes a method for reducing hardware costs in the microprogram Mealy automaton (MPA) scheme implemented on an EMB and LUT basis. The method is based on the use of EMB to implement the logical condition replacement block. It is proposed to implement a part of the output signals (micro-operations) on EMB. The applicability conditions for this approach are shown. An example of the synthesis of MPA using the proposed method is given. All stages of the synthesis are analyzed in detail. Some alternative solutions are proposed and the conditions for their use are shown. Conclusion. Studies have shown that when using one EMB block, our method gives a gain in the number of LUT elements. Comparisons were made with schemes obtained using the Auto, One-hot, and Sequential methods of the Vivado system.

Computing a Group of Polynomials over a Galois Field in FPGA Architecture

For the most extensive range of tasks, such as real-time data processing in intelligent transport systems, etc., advanced computer-based techniques are required. They include field-programmable gate arrays (FPGAs). This paper proposes a method of pre-calculating the hardware complexity of computing a group of polynomial functions depending on the number of input variables of the said functions, based on the microchips of FPGAs. These assessments are reduced for a group of polynomial functions due to computing the common values of elementary polynomials. Implementation is performed using similar software IP-cores adapted to the architecture of user-programmable logic arrays. The architecture of FPGAs includes lookup tables and D flip-flops. This circumstance ensures that the pipelined data processing provides the highest operating speed of a device, which implements the group of polynomial functions defined over a Galois field, independently of the number of variables of the said functions. A group of polynomial functions is computed based on common variables. Therefore, the input/output blocks of FPGAs are not a significant limiting factor for the hardware complexity estimates. Estimates obtained in using the method proposed allow evaluating the amount of the reconfigurable resources of FPGAs, required for implementing a group of polynomial functions defined over a Galois field. This refers to both the existing FPGAs and promising ones that have not yet been implemented.

Application of space vector pulse width modulation algorithm based on programmable logic array in power system

In the traditional power system, the voltage regulation and frequency modulation control method used for boiler induced draft fan is limited in control accuracy. With the improvement of furnace pressure change accuracy, higher requirements are put forward for motor control algorithm. This paper studies permanent magnet synchronous motor (PMSM) as the executive part of induced draft fan servo control system, and adopts FOC control method based on space vector pulse width modulation (SVPWM). Firstly, the simulation model of SVPWM pulse width modulation algorithm is established by MATLAB to provide theoretical support for the subsequent debugging algorithm; When using FPGA to realize SVPWM modulation algorithm, FPGA has the advantages of high reliability and high real-time processing, which provides theoretical support and application guidance for the realization of high-precision motor control of boiler induced draft fan in power system.

Non-blocking programmable delay line with minimal dead time and tens of picoseconds jitter

We report a non-blocking high-resolution digital delay line based on an asynchronous circuit design. Field-programmable gate array logic primitives were used as a source of delay and optimally arranged using combinatorial optimization. This approach allows for an efficient trade-off of the resolution and a delay range together with a minimized dead time operation. We demonstrate the method by implementing the delay line adjustable from 23ns up to 1635ns with a resolution of 10ps. We present a detailed experimental characterization of the device focusing on thermal instability, timing jitter, and pulse spreading, which represent three main issues of the asynchronous design. We found a linear dependence of the delay on the temperature with the slope of 0.2 ps K-1 per logic primitive. We measured the timing jitter of the delay to be in the range of 7-165ps, linearly increasing over the dynamic range of the delay. We reduced the effect of pulse spreading by introducing pulse shrinking circuits and reached the overall dead time of 4-22.5ns within the dynamic range of the delay. The presented non-blocking delay line finds usage in applications where the dead time minimization is crucial, and tens of picoseconds of excess jitter is acceptable, such as in many advanced photonic networks.