Abstract
For the most extensive range of tasks, such as real-time data processing in intelligent transport systems, etc., advanced computer-based techniques are required. They include field-programmable gate arrays (FPGAs). This paper proposes a method of pre-calculating the hardware complexity of computing a group of polynomial functions depending on the number of input variables of the said functions, based on the microchips of FPGAs. These assessments are reduced for a group of polynomial functions due to computing the common values of elementary polynomials. Implementation is performed using similar software IP-cores adapted to the architecture of user-programmable logic arrays. The architecture of FPGAs includes lookup tables and D flip-flops. This circumstance ensures that the pipelined data processing provides the highest operating speed of a device, which implements the group of polynomial functions defined over a Galois field, independently of the number of variables of the said functions. A group of polynomial functions is computed based on common variables. Therefore, the input/output blocks of FPGAs are not a significant limiting factor for the hardware complexity estimates. Estimates obtained in using the method proposed allow evaluating the amount of the reconfigurable resources of FPGAs, required for implementing a group of polynomial functions defined over a Galois field. This refers to both the existing FPGAs and promising ones that have not yet been implemented.
Highlights
To ensure the seamless operation of intelligent transport systems (ITSes), it is required to process large amounts of monitoring information of various formats, purposes, and confidentiality levels in the real-time mode [1,2,3]
Estimates obtained in using the method proposed allow evaluating the amount of the reconfigurable resources of field-programmable gate arrays (FPGAs), required for implementing a group of polynomial functions defined over a Galois field
Several studies [14,15,16] show that the problem of implementing arbitrary maps of one set of elements into another set is reduced to the distributed computation of a group of nonlinear polynomial functions of a given number of variables defined over a Galois field GF (2k ) of a certain power [17]
Summary
To ensure the seamless operation of intelligent transport systems (ITSes), it is required to process large amounts of monitoring information of various formats, purposes, and confidentiality levels in the real-time mode [1,2,3]. The second one is intensive, requiring a flexible adaptation of the CHW hardware to a certain task, rejecting the classical, von Neumann’s, CHW common-bus architecture Unlike the former, the latter way allows implementing devices with higher speeds than that for general-purpose CHW. Several studies [14,15,16] show that the problem of implementing arbitrary maps of one set of elements into another set is reduced to the distributed computation of a group of nonlinear polynomial functions (polynomials, functions) of a given number of variables defined over a Galois field GF (2k ) of a certain power [17]. According to [14,15,16], the separate computation of a group of polynomials involves multiple recomputations of partial polynomial functions common to a group of polynomials This significantly increases the complexity estimates by the number of such IP-cores.
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