Logic Blocks Research Articles

Boolean Minimization of Projected Sums of Products via Boolean Relations

Projected Sums of Products (PSOPs) are a Generalized Shannon Decomposition (GSD) with remainder that restructures a logic function into three logic blocks corresponding to a logic bi-decomposition plus a reminder generated by a cofactoring function. In this paper we discuss a Boolean synthesis technique for PSOPs, which exploits the fact that the resulting logical structure induces don't care conditions that can be exploited to reduce the problem of area minimization to Boolean relation minimization, with the guarantee that all valid realizations of the circuit are considered. This technique is more general than the algebraic methods investigated so far. Moreover, we characterize the points that are in the remainder with a simple procedure that implies a fast construction of the Boolean relation for important classes of cofactoring functions like the chain of XORs or ANDs. We report experiments confirming the effectiveness in area of the proposed approach based on Boolean relations, with better run times for some cost functions.

Design and simulation of priority based dual port memory in quantum dot cellular automata

Design of dual port memory in QCA is an interesting field of study due to concurrent access of data from different ports, although the solution of the data conflict is a changeling task. However, Dual port memory design in QCA is reported in this paper. The architecture is based on the data priority. Priorities of the two ports are generated from the control logic block. Priority bit is required for conditions when the same memory location is requested by both of the ports and at least one operation is the write operation. The functionality of dual port memory is realized with concurrent access of memory array with parallel input-output data lines. Read–Write, Write–Write conflicts are resolved with a priority bit. Priority is uniquely calculated only when both the port request for same memory location access, i.e., the request for concurrent Read–Write or Write–Write operation. When the same memory location is selected, only the signal of the prior port is allowed and of other port is discarded. While the read operation is requested for both the port at same or different memory locations, have no data conflicts and both the ports are allowed to perform read operation. In the proposed architecture, to overcome data conflicts signals of the port having less priority are totally discarded. Significant results of Priority-based 4 × 4 dual port memory are depicted in terms of area and delay. The area, delay, and energy dissipation of Dual port QCA SRAM macro cell are 0.61 µm2, 2.0 clock cycles, and 393.9 meV, respectively. A comparative study of the proposed dual port memory in QCA, single port memory in QCA and dual port memory in CMOS are also performed in this work. The result explored that proposed dual port memory proportionately efficient with respect to the QCA single port memory as well as CMOS dual port memory in terms of area-delay-energy.

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier. In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.

FPGA realization of an efficient image scalar with modified area generation technique

Image scaling is extensively utilized in numerous image processing implementations, like digital camera, tablet, mobile phone, and display devices. Image scaling is a technique of enlarge or diminish the image by provided scale factor. Image scaling can also be discussed as image interpolation, image re-sampling, image resizing, and image zooming. This paper introduces VLSI (Very Large Scale Integration) architecture of an accurate and area effectual image scalar. This architecture is applied in HDL language, synthesize and simulation by Xilinx ISE simulation tool. Lastly observe quality and performance measure, in quality measure associate the PSNR value of scaled image to source image. In presentation measure numerous VLSI parameters like type of device, area, computation time, and power. From the solution in quality measure to upsurge the PSNR value by 15% and 9% Image enlargement and reduction correspondingly and diminish 18% combinational logic blocks (CLBs).

Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block

Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of synchronous circuit is limited by the in phase factor of the clock pulse signal which is used to control the synchronous circuit. In contrast, asynchronous circuits are used widely because it causes low noise, require less power. It affects the less electromagnetic interference that allows reuse of the components. These asynchronous circuits are being implemented by Null Conventional Logic (NCL) which is a delay insensitive logic model. The Configuration Logic Block is the power consuming model in Field Programmable Gate Array (FPGA). This block contains the lookup table (LUT) and 27 fundamental NCL logic gates. To reduce the power consumption of this module, we use the Differential Cascade Voltage Switch Logic (DVSL). The power reduction is achieved in LUT by means of DVSL and minimizes the number transistors. This NCL, DVSL, FPGA logic element is simulated using 90 nm TSMC CMOS processing technology.

Gate-diffusion input (GDI) method for designing energy-efficient circuits in analogue voltage-mode fuzzy and QCA systems

In this work, CNTFET-based GDI (CNT-GDI) and QCA-based GDI (QCA-GDI) methods (CNT/QCA-GDI) for designing unique ultra-efficient analogue and logical blocks in voltage-mode fuzzy and quantum systems are presented. Extensive Monte-Carlo simulations by using Synopsys H-SPICE simulator at 16 nm technology demonstrate that the analogue blocks improve considerably in term of performance, absolute error and energy consumption in the presence of compact variations in compared to their counterparts. Also, the logical blocks have advantages including fast response, high polarity and lower power-consumption achieved by the QCADesigner and QCAPro tools at 18 nm in contrast to the similar designs. As applications, the half wave rectifier (HWR) and full-wave rectifier (FWR) by employing the proposed methods in two technologies are implemented. The results show improvement for the proposed circuits with correct function and very high robustness under major variations in contrast to state-of-the art rectifier architectures at similar conditions. Consequently, the proposed methods are appropriate for designing integrated circuits (ICs) with higher capacity and energy-efficient for the emerging nano-technologies.

A true random number generator architecture based on a reduced number of FPGA primitives

This paper reports on the design, realization and characterization of a True Random Number Generator (TRNG) that operates using as seeds of entropy, the jitter and the metastability introduced by primitives of a Field Programmable Gate Arrays (FPGA) board. In particular, the TRNG architecture has been implemented on a Xilinx Ultrascale XCKU040 FPGA board. Generally, the implementations on FPGA of fully-digital TRNGs make use of ring oscillators employing a large number of Look-Up-Table (LUT) blocks. Differently from this approach, this paper demonstrates that a reliable FPGA-based TRNG architecture can be realized mainly employing only a single PLL and three on-board primitives together with other few basic logic elements (i.e., 8 D-type Flip-Flop, 17 LUT and 2 Counters) used only for the initial overall system synchronization and post-processing operations. In this way, the proposed solution largely reduces the employed number of the FPGA Configurable Logic Blocks (CLB), the circuitry complexity and the overall power consumption without affecting the achievable output bit rate so resulting suitable for full-custom VLSI implementations. The random and statistical properties of the generated 100 Mbps output bitstreams have been validated by passing all the National Institute of Standards and Technology (NIST) tests as well as the Anderson-Darling and the Kolmogorov-Smirnov tests so demonstrating that the proposed TRNG architecture can be suitably employed in security/cybersecurity network systems as well as, once integrated, in Internet-of-Things (IoT) and Industrial-Internet-of-Things (IIoT) applications.

A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash Memory

3-D flash memory faces a number of challenges, including thermal issues and process variation. The high temperature will cause charge loss and lead to the fluctuation of threshold voltage. To address the thermal issue of 3-D flash memory, this paper presents ThermAlloc , a novel thermal-aware physical space allocation strategy for open-channel solid-state drive with 3-D charge trapping flash memory. ThermAlloc permutes the allocation of physical blocks. Consecutively accessed logical blocks are distributed to different physical locations in order to prevent the accumulation of hotspots. The objective is to postpone garbage collection operations and keep the distribution of block temperature well under control. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that ThermAlloc can reduce the peak temperature by 26.94% with 3.15% extra worst-case response time in comparison with the baseline scheme.

Constructing Low-latency Involutory MDS Matrices with Lightweight Circuits

MDS matrices are important building blocks providing diffusion functionality for the design of many symmetric-key primitives. In recent years, continuous efforts are made on the construction of MDS matrices with small area footprints in the context of lightweight cryptography. Just recently, Duval and Leurent (ToSC 2018/FSE 2019) reported some 32 × 32 binary MDS matrices with branch number 5, which can be implemented with only 67 XOR gates, whereas the previously known lightest ones of the same size cost 72 XOR gates.In this article, we focus on the construction of lightweight involutory MDS matrices, which are even more desirable than ordinary MDS matrices, since the same circuit can be reused when the inverse is required. In particular, we identify some involutory MDS matrices which can be realized with only 78 XOR gates with depth 4, whereas the previously known lightest involutory MDS matrices cost 84 XOR gates with the same depth. Notably, the involutory MDS matrix we find is much smaller than the AES MixColumns operation, which requires 97 XOR gates with depth 8 when implemented as a block of combinatorial logic that can be computed in one clock cycle. However, with respect to latency, the AES MixColumns operation is superior to our 78-XOR involutory matrices, since the AES MixColumns can be implemented with depth 3 by using more XOR gates.We prove that the depth of a 32 × 32 MDS matrix with branch number 5 (e.g., the AES MixColumns operation) is at least 3. Then, we enhance Boyar’s SLP-heuristic algorithm with circuit depth awareness, such that the depth of its output circuit is limited. Along the way, we give a formula for computing the minimum achievable depth of a circuit implementing the summation of a set of signals with given depths, which is of independent interest. We apply the new SLP heuristic to a large set of lightweight involutory MDS matrices, and we identify a depth 3 involutory MDS matrix whose implementation costs 88 XOR gates, which is superior to the AES MixColumns operation with respect to both lightweightness and latency, and enjoys the extra involution property.

Constructing Low-latency Involutory MDS Matrices with Lightweight Circuits

MDS matrices are important building blocks providing diffusion functionality for the design of many symmetric-key primitives. In recent years, continuous efforts are made on the construction of MDS matrices with small area footprints in the context of lightweight cryptography. Just recently, Duval and Leurent (ToSC 2018/FSE 2019) reported some 32 × 32 binary MDS matrices with branch number 5, which can be implemented with only 67 XOR gates, whereas the previously known lightest ones of the same size cost 72 XOR gates.In this article, we focus on the construction of lightweight involutory MDS matrices, which are even more desirable than ordinary MDS matrices, since the same circuit can be reused when the inverse is required. In particular, we identify some involutory MDS matrices which can be realized with only 78 XOR gates with depth 4, whereas the previously known lightest involutory MDS matrices cost 84 XOR gates with the same depth. Notably, the involutory MDS matrix we find is much smaller than the AES MixColumns operation, which requires 97 XOR gates with depth 8 when implemented as a block of combinatorial logic that can be computed in one clock cycle. However, with respect to latency, the AES MixColumns operation is superior to our 78-XOR involutory matrices, since the AES MixColumns can be implemented with depth 3 by using more XOR gates.We prove that the depth of a 32 × 32 MDS matrix with branch number 5 (e.g., the AES MixColumns operation) is at least 3. Then, we enhance Boyar’s SLP-heuristic algorithm with circuit depth awareness, such that the depth of its output circuit is limited. Along the way, we give a formula for computing the minimum achievable depth of a circuit implementing the summation of a set of signals with given depths, which is of independent interest. We apply the new SLP heuristic to a large set of lightweight involutory MDS matrices, and we identify a depth 3 involutory MDS matrix whose implementation costs 88 XOR gates, which is superior to the AES MixColumns operation with respect to both lightweightness and latency, and enjoys the extra involution property.

Multi‐objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs

Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g. power and delay. In this study, the authors present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. They address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. The authors’ new approach has been validated using the ‘Golden 20’ MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this study achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. The key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance.

Methods for automated formation of a disassembled listing structure

The subject of the research is the method of splitting a disassembled code into logical blocks in automatic mode, searching for software vulnerabilities without using source code (using a binary file or its equivalent, obtained by reverse engineering).The object of the research is the existing code analyzers and features of their functionality.The aim of the study is to consider the possibility of splitting a disassembled code into logical blocks in automatic mode and some of the possible difficulties associated with this.Formulation of the problem. The complexity of analyzing large software products at the level of machine code necessitates the automation of this process. The research methodology is based on a combination of theoretical and empirical approaches using the methods of static and dynamic analysis, comparison, generalization, algorithmization, modeling, synthesis. Key findings. Splitting the code into blocks by sequential in line-by-line analysis of machine code in some cases can lead to misinterpretation. In addition, the analysis of the code according to the conclusions of the functions also does not guarantee the correctness of the determination of the boundaries of the functions. However, in general, the matrix method can be applied to analyze the dependencies of functions on the blocks of code thus selected.The scientific novelty is connected with the determination of promising vectors for the study of software code for vulnerability, the rationale for the approach (building the transition matrix from integer values), which may be the initial stage of preparation for the automated analysis of the disassembled code.

COFFE 2

FPGAs are becoming more heteregeneous to better adapt to different markets, motivating rapid exploration of different blocks/tiles for FPGAs. To evaluate a new FPGA architectural idea, one should be able to accurately obtain the area, delay, and energy consumption of the block of interest. However, current FPGA circuit design tools can only model simple, homogeneous FPGA architectures with basic logic blocks and also lack DSP and other heterogeneous block support. Modern FPGAs are instead composed of many different tiles, some of which are designed in a full custom style and some of which mix standard cell and full custom styles. To fill this modelling gap, we introduce COFFE 2, an open-source FPGA design toolset for automatic FPGA circuit design. COFFE 2 uses a mix of full custom and standard cell flows and supports not only complex logic blocks with fracturable lookup tables and hard arithmetic but also arbitrary heterogeneous blocks. To validate COFFE 2 and demonstrate its features, we design and evaluate a multi-mode Stratix III-like DSP block and several logic tiles with fracturable LUTs and hard arithmetic. We also demonstrate how COFFE 2’s interface to VTR allows full evaluation of block-routing interfaces and various fracturable 6-LUT architectures.

A New Approach of an Error Detecting and Correcting Circuit by Arithmetic Logic Blocks

This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.

An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST

In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs

A logic synthesis for finite-state machines (FSMs) aimed at programmable array logic (PAL)-based complex programmable logic devices is proposed here. This approach consists of the simultaneous synthesis of a transition function and an output function. The main contribution is the novel multilevel optimization of an FSM. In this process, a new form of graph is used, i.e., a graph of excitations and outputs. This is a generalization of the graph of outputs that has previously been used in the process of technology mapping of multi-output functions in PAL-based programmable structures. The main idea, the theoretical background, and a precise algorithm are illustrated by means of simple examples. The proposed algorithm was compared with other approaches by synthesizing the FSM benchmarks and mapping the solutions to $k$ -term PAL-based logic blocks. The obtained results are compared on the basis of the area (number of logic blocks) and speed (number of logic levels). The proposed approach is especially effective for larger FSMs.

Development of Reversible Programmable Gate Array

The model of digital computation used until now is intrinsically irreversible. This is because the two-bit gates used to construct circuits are irreversible as they involve two input bits and only one output bit. Irreversible gates dissipates energy during their operations, in this manner information bits are lost. Reversible Logic is a technique that can lead to circuits run as normal Logic operations, but use less power. In reversible logic the number of inputs and number of outputs must be equal. The input states are reconstructed from output states because of one to one mapping.Using reversible logic gates in the digital circuits it reduces the power consumption and non-destruction of information. In this paper, configurable logic block is designed in reversible manner for Programmable logic array based and multiplexer based field programmable gate array with less number of reversible gates, garbage outputs and quantum cost.

FPGA as a Hardware Accelerator for Computation Intensive Maximum Likelihood Expectation Maximization Medical Image Reconstruction Algorithm

The major requirements of a good tomographic reconstruction algorithm are a reduction in radiation dosage, accurate reconstruction, detail enhancement, and rapid reconstruction time. Some of these factors are covered by many algorithms but are not collectively addressed in one. While the Maximum Likelihood Expectation Maximization (MLEM) algorithm fares well on many of these factors, it is difficult to apply this algorithm in real-time due to its long execution time. Our predetermined goal is to reduce the execution time to a large extent so that the MLEM’s advantages can be leveraged by using hardware accelerators such as Field Programmable Gate Arrays (FPGA). The FPGAs are becoming especially popular as hardware accelerators and are well known for their programmability, configurability, and massive parallelism through a large number of Configurable Logic Blocks (CLBs). Although FPGAs are extremely versatile, they require complex languages like Verilog or VHDL to program them, incorporating changes in the design level at a later stage in FPGAs demands increased effort. Here, in this paper, for the first time, we present a parallel structure for hardware acceleration of the MLEM on the mammoth Virtex 7 $VC$ 709 FPGA. Using available tools, we also present a programming flow to design the algorithmic acceleration hardware architecture. The proposed flow does not require prior knowledge of the traditionally cumbersome Hardware Description Languages (HDLs) and this makes post design changes very easy to incorporate and validate. The parallel architecture is implemented on an FPGA operating at 220 MHz and we have achieved a $288\times $ performance compared to an optimized software execution on an Intel Xeon workstation with 12-cores 3.1 GHz 32 GB RAM and 12 MB Cache architecture.

Address Translation Layer for Byte-Addressable Non-Volatile Memory-Based Solid State Drives

Because of the need for processing and managing the massive amounts of big data in smart/wearable devices and driverless vehicles, semiconductor companies are focusing on developing byte-addressable non-volatile memory (NVM)-based storage systems. The byte-addressable NVMs, such as phase-change memory, resistive memory, and magnetoresistive memory, are regarded as an alternative to NAND flash memories. There have been many proposals and studies on the use of NVM as main memory in the memory hierarchy. However, there has not been much academic research on using NVM as a substitute for NAND flash memories. This paper provides a system architecture for an NVM-based solid state drive based on some speculations/assumptions on the hardware characteristics of NVMs. It applies the previously proposed address-mapping algorithms of conventional solid state drives to the NVM-based solid state drives and examines their suitability. The optimization of I/O parallelism of static and dynamic address mapping algorithms is compared and analyzed. This paper also observes the effect of log block policies on the hardware characteristics of the NVMs.

In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC)

‘Computations inside Memory’ has become a latest area of research as ‘memory with computing skills’ accelerates the chances of developing ‘beyond-Von Neumann machines’, that is believed to be advantageous in terms of performance and energy-efficiency. ‘Memristors’ are considered as potential devices for building such memories, as they are highly dense, non-volatile scalable devices with faster switching times and lower energy dissipation and are also compatible with the existing CMOS-technology. Additionally, memristors fit in crossbar structure and can perform logic-computations, when different voltages are applied across them. Previously, various synthesis works have been reported for logic realization using memristors. But logic blocks, implemented using synthesis tools, are not always completely optimized. In this context, we present the alternative memristive-designs for the two most commonly used digital units—Delay (D) and Toggle (T) flip-flops. The proposed designs are based on Memristor Aided loGIC (MAGIC) design style and are specific to crossbar-based pure memristive-memories. A relevant simulation methodology is presented for simulating the proposed MAGIC-designs of D and T flip-flops in Cadence Virtuoso. Comparison with the existing designs of D, T flip-flops (using IMPLY) revealed that both the proposed D, T flip-flops are more performance-efficient (by 28.571%, 20% respectively) and more energy-efficient (by 83.873%, 82.905% respectively) than their corresponding IMPLY-peers. Also, the proposed D, T flip-flops are found to use reduced crossbar areas (by 46.667%, 45% respectively) relative to their counterparts generated using a recent synthesis technique, which makes the designs suitable for massive parallel executions inside memristive-memories of any size.