Local Critical Dimension Uniformity Research Articles

Convolutional Neural Network-Assisted Photoresist Formulation Discriminator Design of a Contact Layer for Electron Beam Lithography.

The photoresist formulation is closely related to the material properties, and its composition content determines the lithography imaging quality. To satisfy the process requirements, imaging verification of extensive formulations is required through lithography experiments. Identifying photoresist formulations with a high imaging performance has become a challenge. Herein, we develop a formulation discriminator of a metal oxide nanoparticle photoresist for a contact layer applied to electron beam lithography. This discriminator consists of convolutional neural network photoresist imaging and formulation classification models. A photoresist imaging model is adopted to predict the contact width of variable formulations, while a formulation classification model is used to classify formulations according to relative local critical dimension uniformity (RLCDU). The verification results indicate that the discriminator can accurately recognize photoresist formulations that simultaneously meet the conditions of contact width and RLCDU, and its feasibility has been demonstrated, providing a valuable reference for the preparation of photoresist materials.

New approach of local critical dimension uniformity improvement for via/contact hole etch with direct current superposition

New approach of local critical dimension uniformity improvement for via/contact hole etch with direct current superposition

Machine Learning Applied to Electron Beam Lithography to Accelerate Process Optimization of a Contact Hole Layer.

Determining the lithographic process conditions with high-resolution patterning plays a crucial role in accelerating chip manufacturing. However, lithography imaging is an extremely complex nonlinear system, and obtaining suitable process conditions requires extensive experimental attempts. This severely creates a bottleneck in optimizing and controlling the lithographic process conditions. Herein, we report a process optimization solution for a contact layer of metal oxide nanoparticle photoresists by combining electron beam lithography (EBL) experiments with machine learning. In this solution, a long short-term memory (LSTM) network and a support vector machine (SVM) model are used to establish the contact hole imaging and process condition classification models, respectively. By combining SVM with the LSTM network, the process conditions that simultaneously satisfy the requirements of the contact hole width and local critical dimension uniformity tolerance can be screened. The verification results demonstrate that the horizontal and vertical contact widths predicted by the LSTM network are highly consistent with the EBL experimental results, and the classification model shows good accuracy, providing a reference for process optimization of a contact layer.

E-beam metrology and line local critical dimension uniformity of thin dry resist films for high numerical aperture extreme ultraviolet lithography

E-beam metrology and line local critical dimension uniformity of thin dry resist films for high numerical aperture extreme ultraviolet lithography

Empirical correlator for stochastic local CD uniformity in extreme ultraviolet lithography

We present experimental evidence for an empirical correlator (or model) for stochastic local CD uniformity (LCDU) of contact holes printed in resist with 0.33-NA EUV lithography. The key component of this correlator is a term that has the “traditional” inverse proportionality to the image log-slope (ILS). We also show that, when the contact CD is close to (one of) the stochastic pattern-failure cliffs (i.e., missing contacts or merging contacts), additional terms need to be added. These terms represent the steep rise in LCDU that is typically observed in the vicinity of these cliffs. We also demonstrate an approach for generating the image-intensity function from which ILS is calculated to obtain the best LCDU correlation result (a procedure which we call “image calibration”). Several experimental LCDU data sets that support the validity of the proposed correlator are presented.

Extreme contact shrink for back end of line connectivity

For the past 50 years, Moore’s law has been well followed by the semiconductor industry. The scaling of transistors and interconnects has been enabled not only by various technological advancements but also by novel patterning approaches. However, in order to keep up with Moore’s law, further shrinking at all levels of the integrated circuit is needed. Among them is the back end of line (BEOL), where increasingly smaller metal pitches require tight specifications for vias connecting metal lines. In this paper, BEOL via shrink options is investigated, targeting the bottom critical dimension (CD) 10.5 nm in order to land on metal pitch 21 nm lines below, while maintaining low defectivity, as well as low global and local CD uniformity (CDU and LCDU, respectively). Approaches to this shrink consist of modifications to the etch chemistry at different levels of the mask etch and liner-assisted shrink, either organic or inorganic. Numerical analysis of CD-scanning electron microscopy (CDSEM) images quantitatively shows the efficiency of different approaches via shrink, together with associated CDU, LCDU, and defectivity values. CDSEM results are supplemented by large-area voltage contrast defectivity and transmission electron microscopy data sets.

Stochastic Modeling and Local CD Uniformity Comparison between Negative Metal-Based, Negative- and Positive-Tone Development EUV Resists

Stochastic Modeling and Local CD Uniformity Comparison between Negative Metal-Based, Negative- and Positive-Tone Development EUV Resists

Investigation into a prototype extreme ultraviolet low-n attenuated phase-shift mask

The low-n attenuated phase-shift mask can strongly improve extreme ultraviolet imaging performance; it enhances contrast by mask 3D mitigation and a phase-shift effect while simultaneously reducing the required exposure dose. The latter happens because the low-n mask gives optimum contrast at more open mask bias values than its Ta-based counterpart. Here, we experimentally verify the imaging physics of the low-n mask. We show that optimum exposure latitude (EL) with the low-n mask is obtained at more open mask bias values compared to the Ta-based reference mask. This leads to dose reductions exceeding 30% for pitch 38-nm regular contact holes (CHs). Initial local critical dimension uniformity (LCDU) data for hexagonal CHs pitch 38 and 40 nm show 15% LCDU improvement with the low-n mask compared to the Ta-based reference. A 16-nm dense lines show a substantial EL increase and dose reduction with the low-n mask compared to the Ta-based case; this can be even further improved by combining the novel mask absorber with asymmetric illumination. As the low-n masks studied here have absolute reflectivities in the range 8% to 15%, side-lobe printing should be carefully monitored. Initial experimental data for pitch 120-nm CHs and simulations on P32 metal clips, show no signs of side-lobe printing. Careful monitoring of stochastic side-lobe printing for various use cases is recommended.

Screening of 193i and EUV lithography process options for STT-MRAM orthogonal array MTJ pillars

Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as the most promising candidate to replace the complementary metal-oxide-semiconductor (CMOS) based memories that are dominating the market in the last few decades. What makes STT-MRAM superior to other memories is the high read and write speeds, non-volatility, good cycling endurance and near-zero leakage. Moreover, with the perpendicular device topology and the single transistor cell configuration, it becomes a very promising candidate for further device scaling which is essential to increase the memory densities. This paper focuses on the experiments performed using different lithography approaches in order to explore the smallest printable pitches for orthogonal array magnetic tunnel junction (MTJ) pillars, which are the main components of the STT-MRAM. Considering the high impact of the MTJ patterning process on the robustness of the memory device, several post-litho performance parameters such as wafer critical dimension uniformity (WCDU), local critical dimension uniformity (LCDU) and pillar circularity have also been measured and compared.

Fundamental characterization of stochastic variation for improved single-expose extreme ultraviolet patterning at aggressive pitch

Background: With aggressive scaling of single-expose (SE) extreme ultraviolet (EUV) lithography to the sub-7-nm node, stochastic variations play a prominent role in defining the lithographic process window (PW). Fluctuations in photon shot noise, absorption, and subsequent chemical reactions can lead to stochastic failure, directly impacting electrical yield. Aim: Fundamental characterization of the mode and magnitude of these variations is required to define the threshold for failure. Approach: A complementary series of techniques is enlisted to probe the nature and modulation of stochastic variation in SE EUV patterning. Unbiased line edge roughness (LER), local critical dimension uniformity (LCDU), and defect inspection techniques are employed to monitor the frequency of stochastic variations leading to failures in line/space (L/S) and via patterning. Results: When characterizing different resists and illumination conditions, there is no change in unbiased LER or via LCDU with increasing critical dimension (CD). Stochastic defect density is correlated with CD for both L/S and via arrays, and there is a strong correlation with L/S electrical yield data. Conclusions: Traditional 3σ LER and via LCDU measurements are not sensitive enough to define and improve PW. For PW centering and yield improvement, stochastic defect inspection is a necessity.

Stochastic printing failures in extreme ultraviolet lithography

Stochastic effects in lithography are known to be the cause of critical dimension (CD) variability, quantified, e.g., by linewidth roughness or local CD uniformity, but—when the CDs are small—they can also lead to printing failures, and hence have a significant impact on yield. We will focus on these printing failures and review three important topics in this relatively new field. First, we will look at how these failures can be detected and show how either CD-SEM, e-beam inspection, and optical defect inspection can play a useful role. Next, we consider the important question of how the stochastic failure probability (which we quantify by a metric we call “Not OK,” abbreviated NOK) depends on the lithography- and process-settings, a question that is of obvious importance when looking for conditions that will minimize the failure probability and hence maximize the yield. Finally, we will discuss to what extent we can fit experimentally observed failure probabilities, to empirical models. Such models can play a vital role in future OPC-verification flows, where screening full mask layouts for “stochastic hot spots” is expected to become a mandatory step.

EUV vote-taking lithography for mitigation of printing mask defects, CDU improvement, and stochastic failure reduction

Vote-taking lithography is a method for mitigating mask defects, which has been applied in the 1980s to enhance yield. Vote-taking sums up N different mask images with identical content, each at 1 / N dose, to mitigate the defects on each individual mask. The fundamental assumption is that the mask defects do not correlate in position from mask to mask, and so each individual defect will be blended with good images from the other N − 1 masks. Vote-taking has recently been reconsidered for extreme ultraviolet (EUV) lithography, where it might provide a temporary solution for situations in which the defectivity conditions are not yet meeting expectations. This paper provides a thorough experimental assessment of the implementation of vote-taking and discusses its pro’s and con’s. Based on N = 4 vote-taking, we demonstrate the capability to mitigate different types of mask defects. We found additional benefits of blending different mask images, distinct from mask defect reduction. Experimental results will be shown that demonstrate improved critical dimension uniformity (CDU), both local CDU and intrafield CDU, reduced overlay errors, and smaller stochastic defect levels. Finally, we perform dedicated throughput calculations based on the qualification performance of ASML’s NXE:3400B scanner. This work must be seen in the light of an open-minded search for options to optimally enable and implement EUV lithography. Although defect-free masks and EUV pellicles are without argument essential for most of the applications, we investigate whether some applications could benefit from vote-taking.

Assessment of pattern variability and defectivity by large-scale SEM metrology with >100 million measurements

We present an experimental study of pattern variability and defectivity, based on a large data set with >112 million critical dimension (CD) and via area measurements from a Hermes Microvision Inc. (HMI) high-throughput e-beam tool. The test case is a 10-nm node static random-access memory via array patterned with a deep ultraviolet immersion litho-etch-litho-etch process, where we see a variation in mean size and litho sensitivities between different unique via patterns that leads to significant differences in defectivity. The large data volume made available by high-throughput inspection capability of the HMI eP5 tool enables analysis to reliably distinguish global and local CD uniformity variations, including a breakdown into local systematics and stochastics. From a closer inspection of the tail end of the distributions and estimation of defect probabilities, we conclude that there is a common defect mechanism and defect threshold despite the observed differences of specific pattern characteristics. In addition, we studied wafer fingerprints for both global CD uniformity (GCDU) and local CD uniformity (LCDU), including stochastics. We used LCDU and GCDU wafer maps to identify correlations between those parameters and defect count. We expect that the analysis methodology presented can be applied for defect probability modeling as well as general process qualification in the future.

Measurement of pattern roughness and local size variation using CD-SEM

Measurement of line edge roughness (LER) is discussed from four aspects: edge detection, power spectrum densities (PSD) prediction, sampling strategy, and noise mitigation. General guidelines and practical solutions for LER measurement today are introduced. Advanced edge detection algorithms such as the wave-matching method are shown to be effective for robustly detecting edges from low SNR images, whereas a conventional algorithm with weak filtering is still effective in suppressing SEM noise and aliasing. An advanced PSD prediction method such as the multitaper method is effective in suppressing sampling noise within a line edge to analyze, whereas a number of lines are still required for suppressing line-to-line variation. Two types of SEM noise mitigation methods, such as the “apparent noise floor” subtraction method and LER-noise decomposition using regression analysis, are verified to successfully mitigate SEM noise from PSD curves. These results are extended to local critical-dimension uniformity (LCDU) measurement to clarify the impact of SEM noise and sampling noise on LCDU.

Stochastics in extreme ultraviolet lithography: investigating the role of microscopic resist properties for metal-oxide-based resists

Due to the high energy of extreme ultraviolet (EUV) photons, stochastic effects become more important at a constant dose when compared with deep ultraviolet exposures. Photoresists are used to transfer information from the aerial image into physical features and play an important role in the transduction of these stochastic effects. Recently, metal-oxide-based nonchemically amplified resists (non-CARs) have attracted a lot of attention. We study how the properties of these non-CARs impact the local critical dimension uniformity (LCDU) of a regular contact hole array printed with EUV lithography using Monte Carlo simulations and an analytical model. We benchmark both the simulations and the analytical model to experimental data, and then use the flexibility of both methods to systematically investigate the role of microscopic resist properties in the final LCDU. It is found that metal-oxide clusters should be <1 nm in diameter, otherwise granularity will have a significant contribution to LCDU. When varying resist properties to change the resist dose-to-size, we find that the LCDU scaling with dose depends on how the resist is modified. After performing an overall sensitivity analysis to identify the optimum scaling of LCDU with dose, we find a scaling of dose − 0.5 when the development threshold is modified, and a scaling of dose − 0.33 when core radius or the quantum efficiency is changed.

Stochastic effects in EUV lithography: random, local CD variability, and printing failures

Stochastic effects in lithography are usually quantified through local CD variability metrics, such as line-width roughness or local CD uniformity (LCDU), and these quantities have been measured and studied intensively, both in EUV and optical lithography. Next to the CD-variability, stochastic effects can also give rise to local, random printing failures, such as missing contacts or microbridges in spaces. When these occur, there often is no (reliable) CD to be measured locally, and then such failures cannot be quantified with the usual CD-measuring techniques. We have developed algorithms to detect such stochastic printing failures in regular line/space (L/S) or contact- or dot-arrays from SEM images, leading to a stochastic failure metric that we call NOK (not OK), which we consider a complementary metric to the CD-variability metrics. This paper will show how both types of metrics can be used to experimentally quantify dependencies of stochastic effects to, e.g., CD, pitch, resist, exposure dose, etc. As it is also important to be able to predict upfront (in the OPC verification stage of a production-mask tape-out) whether certain structures in the layout are likely to have a high sensitivity to stochastic effects, we look into the feasibility of constructing simple predictors, for both stochastic CD-variability and printing failure, that can be calibrated for the process and exposure conditions used and integrated into the standard OPC verification flow. Finally, we briefly discuss the options to reduce stochastic variability and failure, considering the entire patterning ecosystem.

Novel EUV Photoresist for Sub-7 nm Node

Extreme ultraviolet (EUV) lithography has been recognized as a promising candidate for the manufacturing of semiconductor devices as LS/CH pattern for 7 nm node and beyond. EUV lithography is ready for high volume manufacturing stage. For the high-volume manufacturing of semiconductor devices, significant improvement of sensitivity and line edge roughness (LWR) and Local CD Uniformity (LCDU) is required for EUV resist. It is well-known that the key challenge for EUV resist is the simultaneous requirement of ultrahigh resolution (R), low line edge roughness (L) and faster sensitivity (S). Especially sensitivity and good roughness is important for EUV lithography high volume manufacturing. We are trying to improve sensitivity and LWR/LCDU from many directions. From material side, we found that both sensitivity and LWR/LCDU are simultaneously improved by controlling acid diffusion length and efficiency of acid generation using novel resin and PAG. And optimizing EUV integration is one of the good solution to improve sensitivity and LWR/LCDU. We are challenging to develop new multi-layer materials to improve sensitivity and LWR/LCDU. Our new multi-layer materials are designed for best performance in EUV lithography system. From process side, we found that sensitivity was substantially improved maintaining LWR applying novel type of chemical amplified resist (CAR) and process. EUV lithography evaluation results obtained for new CAR EUV interference lithography. And, metal containing resist is one possibility to break through sensitivity and LWR trade off. In this paper, we will report the recent progress of sensitivity and LWR/LCDU improvement of JSR novel EUV resist and process.

(Invited) Vertical Nanowire FET Integration and Device Aspects

Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has provided ever increasing device performance and density. For advanced (sub-)5nm nodes, to keep the growth pace, several options can be considered in terms of material choices, device architectures and circuits design. However, further cells scaling using conventional 2D layouts is becoming more and more challenged by key factors such as the physical limits on gate and contact placement and interconnect routing congestion. Vertical nanowire (VNW) devices appear particularly well placed to overcome some of these limitations, but require early process-design cross-disciplinary interactions to address the technological and design challenges/opportunities of moving from a 2D to a 3D layout configuration for CMOS. In this work, we will address some of these aspects, focusing first on a comparative analysis review of performance, parasitics and layout efficiency between VNWFETs (3D layout) and lateral nanowire (LNW) FETs or finFETs (2D layout), followed by a comprehensive overview of some key integration aspects regarding VNWFET devices fabrication. In VNWFETs, since the gate length (Lgate) is defined vertically, it can be relaxed without area penalty, which in turn also allows some relaxation in the NW diameter, while keeping optimum short-channel-effects control. This is an important advantage of the vertical device architecture as several theoretical studies predict mobility degradation below a certain NW dimension, which would also cancel off the gains of using high-mobility channels such as Ge or III-V over silicon [1,2]. Moreover, Lgate relaxation is an important knob for variability optimization and leakage control, critical in scaled SRAMs. In terms of layout, VNWFETs can enable more compact cells [2,3], for instance by placing two pull-up transistors on the same row of a SRAM cell, saving around 30% area in comparison to a finFET-based SRAM [2]. A comparative simulation analysis in [4] of NAND library cells also suggests promising speed gains and power consumption reduction when switching from a 7nm Si-baseline finFET technology to 5nm Si VNWFETs. In addition, despite their potential for lower parasitic RC, VNWFETs asymmetry for source/drain wiring needs to be taken into account in circuit design and in processing for bottom access resistance optimization [2,5]. From an integration perspective, two main routes can be considered for device fabrication: channel-first or channel-last. In this work, we will focus on the first approach for added flexibility in terms of channel material choice [Si, (Si)Ge, III-V] and also control of the channel (defects) quality. Channel body (NW pillar) definition is done using 193nm immersion lithography followed by dry-etch. For the particular case of III-V, a bottom-up approach can also be considered for the NWs growth [6] (Fig.1). NW diameter (CD) shrinkage by dry-etch is challenged by the local CD uniformity control of the pillars within the NW arrays and their high aspect-ratio. Further CD reduction, and potentially also smoothening of the NW sidewalls, can be obtained by applying n cycles of low-temperature, [O3-oxidation -> oxide etch] for Si-based pillars, digital etch for III-V pillars [7]. With regards to Si NW doping, for simplicity in terms of junction formation, we rely on growing up to three stacked layers of (uniformly doped) Si epi. A wide doping range for a given layer and a sharp doping concentration steepness between doped regions are feasible via tuning of the growth conditions such as pressure and B2H6 flow (for B-doped Si epi, PMOS). For extra simplicity, junctionless type of devices can also be particularly interesting to consider as they do not require junctions [8]. In a vertical device flow, control of the thickness of the different layers surrounding the NW pillars is key (Fig.2), both for a gate-first or a gate-last scheme, the latter enabling further options for device fabrication such as decoupling the gate module from doping/series resistance optimization for the top part of the NW. Here, layout dependences observed for several dry and wet etch processes and specific etch-back challenges (e.g., W surface roughness control) triggered the need for introduction of alternative schemes for improved process control of the layers on the wafers.

Model-based breakdown of resist and mask contributions to local CDU for sub-30-nm contact holes in EUV lithography

The resist and mask contributions to the local critical dimension uniformity (L.CDU) of 30-nm contact holes (CHs) printed using extreme ultra-violet lithography (EUVL) are decomposed quantitatively by three independent budget breakdown methods. An asymptotic behavior model is proposed for the prediction of the resist-only contribution via a shifted and averaged multiple exposure (SAME) method that statistically averages out the collective mask local contributions. The other two budget breakdown methods of assessing, the variance of site-to-site difference for the derivation of resist-only contribution and the global mask error enhancement factor (G.MEEF) for the mask-only contribution, are performed and compared to the resist and mask contributions from the SAME method. The three budget breakdown methods consistently indicate that approximately 75–80% of L.CDU is attributed to the resist and process regardless of the process conditions, such as post exposure bake (PEB) temperature, PEB time, and exposure dose. L.CDU exhibits a linear correlation with 1/sqrt(dose), which is a potential indication that photon shot noise (PSN) could be a key contributor to the L.CDU on a wafer. Although a significant reduction of the total L.CDU is observed in the low PEB temperature process, i.e., high exposure dose, a relatively small change in the ratio of the resist-to-mask contribution may be observed because the chemical contrast enhancement by acid diffusion reduction is relatively small compared to PSN reduction.

Progresses and Challenges of EUV Lithography Materials

In the last years the continuous efforts on the development of EUV lithography has allowed to push the lithographic performances of the EUV photoresists on the ASML NXE:3100 full field exposure tool at imec. The latest chemically amplified photoresists can reach an ultimate resolution of 16 nm and 24 nm for line-space (L/S) and dense contacts (CH), respectively, but the major issue on EUV photoresists remains to simultaneously meet resolution, sensitivity, line-edge roughness (LER) for LS and local CD uniformity (LCDU) for CH, suggesting that the desired performance characteristics of EUV photoresists may require the development of new EUV materials. Aiming to this, imec has recently started a new project to look into novel materials for EUV lithography to explore alternative approaches that can offer superior characteristics in photoresist imaging: improved LER and line collapse, high sensitivity and high etch resistance. In this paper we report the first results from the exploration of new EUV alternative materials and the latest results from the conventional EUV photoresist evaluation and process optimization at imec towards the ASML NXE:3300 full field exposure tool.