Abstract
For the past 50 years, Moore’s law has been well followed by the semiconductor industry. The scaling of transistors and interconnects has been enabled not only by various technological advancements but also by novel patterning approaches. However, in order to keep up with Moore’s law, further shrinking at all levels of the integrated circuit is needed. Among them is the back end of line (BEOL), where increasingly smaller metal pitches require tight specifications for vias connecting metal lines. In this paper, BEOL via shrink options is investigated, targeting the bottom critical dimension (CD) 10.5 nm in order to land on metal pitch 21 nm lines below, while maintaining low defectivity, as well as low global and local CD uniformity (CDU and LCDU, respectively). Approaches to this shrink consist of modifications to the etch chemistry at different levels of the mask etch and liner-assisted shrink, either organic or inorganic. Numerical analysis of CD-scanning electron microscopy (CDSEM) images quantitatively shows the efficiency of different approaches via shrink, together with associated CDU, LCDU, and defectivity values. CDSEM results are supplemented by large-area voltage contrast defectivity and transmission electron microscopy data sets.
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