Lithography Solutions Research Articles

PECVD Bi-Layer ARC for BARC-less Immersion Lithography

A PECVD bi-layer Dielectric Anti-Reflective Coating (DARC®) process has been developed as a cost-effective solution for immersion lithography. The proposed bi-layer DARC scheme eliminates the need for a Bottom Anti-Reflective Coating (BARC) which is commonly used in both dry and immersion lithography processes, thereby reducing manufacturing cost and improving etch margin for better CD control. The bi-layer DARC film properties are highly tunable for different underlayers to provide optimal reflectivity control. With the bi-layer DARC scheme, we have demonstrated a minimum line width of 30 nm with a wider process window and comparable line edge roughness (LER) as a BARC scheme. The patterning performance is stable after multiple rework cycles and extended queue time, proving the manufacturability of the bi-layer DARC process.

Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration

Abstract: The performance of the manufacturing process in each of these areas determines the overall manufacturability of the process. As device geometries are reduced, understanding and minimising the sources of process‐induced defects is critical to achieving and maintaining high device yields. This paper presents a comprehensive investigation of a novel metrology on semiconductor process module integration and technology on optimal integrated lithography processes and solution to the problem of defects reduction on semiconductor wafer in sub‐micron processes integration. As dual damascene integration copper process is complicated and critical in semiconductor processes. It has been common knowledge that pattern collapse and missing of this process and numerous defects could be prevented by optimal the process module tuning. To investigate novel semiconductor process integration on deep pattern aspect ratio effects of sub‐micron semiconductor wafer BEOL (Back‐End‐Of‐Line) structure were included in this study. Moreover, the electrical device investigations of device checking were also included.

Metallic and dielectric photonic crystals with chiral elements by combined nanoimprint and reversal lithography in SU-8

We report a novel nanoprocess combining nanoimprint lithography and conventional lithography to fabricate metallic and dielectric nanophotonic crystals with chiral elements in SU-8. The previously developed nanoimprint process was modified for much smaller feature size. Four different types of nanophotonic crystals with different materials in both large and small dimensions are fabricated. The new proposed reversal lithography is used to fabricate one type among the above mentioned four. The success of reversal lithography provides a solution for near-field lithography to achieve nanosize structures with simple conventional lithography. Optical measurements of the laser polarization state from the fabricated photonic crystals indicate an optical chirality which distinguishes the chiral elements from other normal symmetric structures.

Extendability of 193nm immersion lithography

There are now commercially-available 193nm water immersion scanners with numerical apertures (NAs) of 1.3 or 1.35. They can provide lithography solutions for line-and-space features as small as 45nm half-pitch. Can they be extended to provide 32nm half-pitch lithography? A simple k1-calculation suggests that a 193nm scanner with NA at least of∼1.65 is needed to print 32nm dense lines in which the width of the lines and spaces between them are equal (i.e., 1:1). A further increase of NA beyond 1.35, however, is limited by the refractive index (RI) of the system’s lens, fluid, and resist. Therefore, the development of high-RI materials is key. Here, we will discuss the requirements for each material in more depth after discussing the scanner system as a whole.

Present status and future prospects of LEEPL

Intensive efforts to develop LEEPL tools and to build the infrastructure supporting LEEPL technology have been made since the concept of LEEPL was first published in 1999. As a result, LEEPL has been recently gaining recognition as a potential solution for future lithography in semiconductor industry. Here, LEEPL’s present status and future prospects are presented on the basis of these efforts.

Transitioning of direct e-beam write technology from research and development into production flow

The electron beam direct write (EBDW) lithography solution is already mature enough to be used for semiconductor manufacturing. This paper illustrates the potential of EBDW to support technology development as a patterning technique complementary to the projection optical lithography. The first classical application of EBDW lithography is to support the research and development efforts (R&D) well before the optical scanners with required resolution are available. EBDW can potential lower the cost of manufacturing by eliminating very expensive masks for critical layers. Benefits of mask less solution in terms of cycle time, flexibility is presented through integration examples confirming the potential of this technique for semiconductor manufacturing.

Nano-imprint lithography: Templates, imprinting and wafer pattern transfer

Nano-imprint lithography is attracting attention as a low cost method for printing nanometer-scale geometries and has obtained placement on the International Technology Roadmap for Semiconductors as a potential lithography solution at the 32 and 22 nm fabrication nodes [International Technology Roadmap for Semiconductors, 2003 ed.]. As a result, nano-imprint technology and infrastructure development related to template infrastructure, imprinting capabilities, and wafer-level pattern transfer processes are essential to successfully make the transition from research and development to a viable manufacturing processing technique suitable for multiple applications. Motorola Labs has been focusing on developing the template and wafer-level processes while optimizing the imprinting process and collaborating with external partners to optimize both the inspection and repair of imprint templates. This paper reviews recent results of the above-mentioned focus areas.

Optical Lithography for the 32nm Node

The 32nm lithography node is the next major target for optical lithography on the Semiconductor Industry Roadmap. The recently developed water-based immersion lithography using ArF illumination will be able to provide an optical solution for lithography at the 45nm node, but it cannot achieve the 32nm node as currently defined. EUV is the main solution for the 32nm node, but the evolution of immersion lithography does represent an opportunity to extend ArF lithography down to the 32nm node.This paper reports progress towards achieving 32nm lithography using immersion lithography. To achieve this next lithographic node will require new, very high refractive index fluids to replace the water used in current immersion systems.Testing and experiments to develop key technology for the 32nm node are reported. These experiments were run using interference immersion lithography.Interference imaging printers have been available for years, and with the advent of immersion lithography have a new use. Interference immersion image printing offers the user a rapid, cost-effective way to develop immersion lithography, particularly at extremely high resolutions. Although it can never replace classical lens-based lithography systems for semiconductor device production, it does offer a way to develop resist and fluid technology at a relatively low cost. Its simple, image-forming format offers easy access to the basic physics of advanced imaging. Issues such as: fluid/resist interaction during exposure; topcoat film performance; line edge roughness of resists at extremely high resolutions; and the polarization of the image-forming light rays can all be readily studied.Experiments are described and results are provided for work on: 32nm imaging tests; high refractive index fluid testing using ArF wavelength at resolutions well beyond current lens-based system capabilities; and polarization configuration testing on both 32nm and 45nm L/S features.

Immersion lithography: New opportunities for semiconductor manufacturing

Immersion lithography has recently emerged as the preferred lithography solution for manufacturing the next generation of semiconductor devices (likely to address the 65, 45, and possibly the 32nm nodes). Full-field immersion scanners operating at λ=193nm with de-ionized water as the immersion fluid have been recently demonstrated. In this article we report imaging results from the AT1150i prototype, a 0.75 numerical-aperture full-field scanner from ASML. We experimentally confirm the depth-of-focus improvements that immersion enables, and explore the implications of this gain for semiconductor manufacturing. This article also highlights the challenges the technology faces before it can be successfully introduced for semiconductor manufacturing. We pay particular attention to defects, in the form of particles, bubbles, and other processing residues, and highlight evaporation as a key mechanism underpinning these challenges.

Enabling alternating phase shifted mask designs for a full logic gate level

The International Technology Roadmap for Semiconductors lists F2 (157 nm exposure wavelength) optical lithography and extreme ultraviolet (EUV) next generation lithography as the two most feasible lithography solutions for the 70 nm technology node. It is very likely that both of these lithography solutions will be late, forcing ArF (193 nm exposure wavelength) lithography to operate at unprecedented resolution levels. Lithographically, alternating phase shifted masks (altPSM) can achieve the resolution required to manufacture 70 nm logic products with ArF lithography equipment [P. Schiavone, F. Lalanne, and A. Prola, Clear field alternating PSM for 193 nm lithography, Proc. SPIE 3679, 582-589 (1999) and M. Fritz et al., Application of chromeless phase-shift masks to sub-100 nm SOI CMOS transistor fabrication, Proc. SPIE 4000, 388-407 (2000)], but technical and logistical challenges associated with the broad implementation of altPSM require novel and invasive EDA solutions which have caused the industry to shy away from altPSM in the past. Since the resolution capabilities of altPSM are well understood in the lithography community, this paper will focus on the challenges facing altPSM implementation for the polysilicon gate level and will present the results of a detailed altPSM design feasibility study done at IBM for the 180 nm technology node. While the 70 nm technology node will push resolution harder then ever before, the design rules, EDA tools, and layout methodologies developed in the past lay the foundation for our attack on this challenging technology node.

CMOS and beyond

Lithography has played a key role in the scaling of CMOS-based integrated circuits. To fabricate sub-70 nm features, new techniques based on electron projection and extreme ultraviolet radiation are being developed. These and other lithographic solutions are discussed. For the ultimate in scaling, an alternate approach would be to start with objects that are inherently nano-scale in size, and use chemical techniques to have these objects self-assemble into units that provide electronic functionality. Several classes of molecules, including carbon nanotubes, deoxyribonucleic acid (DNA) and custom-synthesized organic molecules, are potentially suitable for this approach. Some recent advances in their research will be reviewed.

Synchrotron light as a source for extreme ultraviolet lithography

In August 1998 a new European research program named Extreme Ultraviolet Concept Lithography Development System (EUCLIDES) was started. The program headed by ASM Lithography (ASML), partnered by Carl Zeiss and Oxford Instruments is evaluating extreme ultraviolet (EUV) light as a viable lithographic solution for resolutions of 70 nm and below. Oxford Instruments has investigated various options to use as synchrotron light sources: bending magnets, undulators, and wigglers. Output characteristics are given in terms of angular distribution and power spectrum. It will be explained wigglers are the preferred synchrotron light. The outline design of the storage ring is presented. The lattice is reviewed together with the light output properties and space requirements. How these drive the cost of ownership is addressed. Finally a brief comparison is made between this and the alternative (laser plasma) sources for EUV.

EUCLIDES: European EUVL Program

In August 1998 a new European research program named extreme ultraviolet concept lithography development system (EUCLIDES) was started. The program, headed by ASM Lithography (ASML), partnered by Carl Zeiss and Oxford Instruments, is evaluating extreme ultraviolet lithography (EUVL) as a viable lithographic solution for resolutions of 70 nm and smaller. In this article a summary of program objectives and status will be given, followed by an overview of recent highlights obtained by the various program partners and subcontractors. Results of the system architecture study will be presented. These include the (preliminary) results of the comparison study between laser plasma and synchrotron sources in terms of throughput and cost-of-ownership. A novel technique will be presented which mitigates resist outgassing without the need of a window between the projection optics and the wafer. Using this idea the EUV flux on the wafer can be doubled hence increasing the throughput. An EUVL test bench, containing an EUV interferometer is under construction. The test bench contains an operational water droplet laser plasma source. Experimental results will be presented. Part of the program focuses on optical and mechanical design, substrate fabrication, metrology, and multilayer coatings. Most recent results on coatings and optical substrate manufacturing will be presented.

Experimental Studies on the Toxicity of Lithographic Developer Solution

The purpose of this study was to determine whether the toxicity of a lithographic developer solution which contains hydroquinone is caused by hydroquinone or the alkaline lithographic developer solution. Male Wistar rats were divided into seven groups. In four groups, rats were dosed orally with 3% hydroquinone or 3% hydroquinone in 3% lithographic developer solution. Hydroquinone levels were measured after one and 24 hours. In two groups, rats were dosed orally with 6% hydroquinone or 6% hydroquinone in lithographic developer solution. In the seventh group, rats received the alkaline solution only. Hydroquinone measurement was made using gas chromatography-mass spectrometry. Hydroquinone was rapidly absorbed from the gastrointestinal tract and subsequently distributed throughout the body. Nearly all hydroquinone was excreted in the urine as either a glucuronide or a sulfate (78-82%) within 24 hours. All rats administered 6% hydroquinone in non-alkaline vehicle died, but the mortality rate of rats administered 6% hydroquinone in lithographic developer solution was 60%. Tissue hydroquinone was lower at one hour and 24 hours after administration in lithographic developer solution than in equal dose of hydroquinone in non-alkaline vehicle suggesting decreased absorption in an alkaline pH. Hydroquinone was not associated with gross pathologic changes of the intestine but all animals treated with lithographic developer solution or alkaline solution had congestion, hemorrhagic petechiae and purple-brown discoloration throughout the small intestine. The combination of alkaline/formaldehyde diluent with hydroquinone may delay hydroquinone absorption but increase the risk of intestinal necrosis.

Dry etching for silylated resist development

Dry developable resist systems based on silylation have been presented as an alternative solution for submicron and deep submicron lithography. The DESIRE process (Diffusion Enhanced Silylated Resist) is the most well-known example of such a process. In this paper the dry development step using reactive ion etching has been investigated using a TEGAL MCR (magnetically confined reactor). The MCR system is a versatile tool which provides two major improvements over classical RIE: the magnetical confinement of the plasma and the triode RF coupling system.In this paper the influence of the pressure, the bias power and the oxygen flow on the etch rate and the shape of the photoresist pattern was investigated. The etch rate of the resist and associated uniformity depend on the plasma etching parameters. The exposure dose is however the major parameter determining the critical dimension (CD).