Enabling alternating phase shifted mask designs for a full logic gate level

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The International Technology Roadmap for Semiconductors lists F2 (157 nm exposure wavelength) optical lithography and extreme ultraviolet (EUV) next generation lithography as the two most feasible lithography solutions for the 70 nm technology node. It is very likely that both of these lithography solutions will be late, forcing ArF (193 nm exposure wavelength) lithography to operate at unprecedented resolution levels. Lithographically, alternating phase shifted masks (altPSM) can achieve the resolution required to manufacture 70 nm logic products with ArF lithography equipment [P. Schiavone, F. Lalanne, and A. Prola, Clear field alternating PSM for 193 nm lithography, Proc. SPIE 3679, 582-589 (1999) and M. Fritz et al., Application of chromeless phase-shift masks to sub-100 nm SOI CMOS transistor fabrication, Proc. SPIE 4000, 388-407 (2000)], but technical and logistical challenges associated with the broad implementation of altPSM require novel and invasive EDA solutions which have caused the industry to shy away from altPSM in the past. Since the resolution capabilities of altPSM are well understood in the lithography community, this paper will focus on the challenges facing altPSM implementation for the polysilicon gate level and will present the results of a detailed altPSM design feasibility study done at IBM for the 180 nm technology node. While the 70 nm technology node will push resolution harder then ever before, the design rules, EDA tools, and layout methodologies developed in the past lay the foundation for our attack on this challenging technology node.