Lightly Doped Drain Research Articles

Application of fluorine doped oxide (SiOF) spacers for improving reliability in low temperature polycrystalline thin film transistors

The novel process of self-aligned fluorine doped oxide (SiOF) spacers on low temperature poly-Si (LTPS) lightly doped drain (LDD) thin film transistors (TFTs) is proposed. A fluorine doped oxide spacers were provided to generate the lower dissociation Si–F bonds adjusted to the interface of the drain which is the largest lateral electric field region for lightly doped drain structure. The stronger Si–F bonds can reduce the bonds broken by impact ionization. It is found that the output characteristics of SiOF spacers TFTs show the superior immunity to kink effect. The degradations in Vth shifting, subthreshold slope, drain current and transconductance of SiOF spacers after DC stress are improved.

The Channel Length Extension in Poly-Si TFTs With LDD Structure

In this letter, the resistance of the lightly doped drain (LDD) region in n-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) was analyzed. It was found that the LDD resistance was composed of an LDD-length-dependent part and a gate-bias-dominant part. The latter was located next to the gate edge and was governed by the channel extension phenomenon with an extended length of around 0.55 mum under a 10-V gate bias. The current density distribution simulated by Silvaco ATLAS supported this severe fringing field effect. The influences of the gate bias, LDD doping level, gate oxide thickness, and LDD length on the channel extension are also investigated with Silvaco ATLAS simulation. This letter is the first report of long channel extensions in the LDD region of poly-Si TFTs. The result may significantly influence the device model in the short channel regime.

Device Physics and Performance Optimization of Impact-Ionization Metal–Oxide–Semiconductor Transistors formed using a Double-Spacer Fabrication Process

In this paper, the impact-ionization metal–oxide–semiconductor (I-MOS) transistor structure is further optimized by utilizing a double-spacer fabrication process. This novel fabrication process allows for performance optimization through independent tuning of four individual implants which form a shallow source region, a lightly-doped drain region, a heavily-doped drain region, and a deep source region. The performance optimization is guided by detailed understanding of the device physics and will be described. The breakdown voltage needed for avalanche breakdown is optimized using the shallow source extension, and the lightly-doped drain extension reduces the impact of drain bias on breakdown voltage and hence the threshold voltage. The heavily-doped drain and deep source implants reduce the parasitic series resistance of the transistor. The double-spacer I-MOS is fabricated and characterized. Detail analysis and physical explanation of the impact of drain/gate bias on the device characteristics will be given. In addition, excellent subthreshold swing and good device performance are achieved.

An Optimized Scalable BSIM Macromodel for HV Double-Diffused Drain MOSFET ${I}$–${V}$ Characteristics

This letter presents a scalable macromodel dedicated to the I-V characteristics of the high-voltage double diffused drain metal oxide semiconductor field effect transistor (MOSFET), which can be widely used in SPICE simulators and electronic design automation tools. The scalable model has been validated for different device geometries: large dimension (L = 20 mum, W = 20 mum), narrow dimension (L =20 mum, W = 1.8 mum/2 mum/5 mum), and short dimension (L = 1.2 mum/1.5 mum/2 mum/3 mum/5 mum, W = 20 mum). The variable-resistance feature of the lightly-doped drain has been simulated by metal semiconductor FET and diode, instead of by variable resistance which the Berkeley short channel insulated gate field effect transistor model (BSIM) does not support. This approach not only improves the utility value of the macromodel, but also considers the physical effects of the high-voltage MOSFET. Furthermore, this scalable macromodel can be applied to the modeling software tools based on the SPICE BSIM model.

A Double-Spacer I-MOS Transistor With Shallow Source Junction and Lightly Doped Drain for Reduced Operating Voltage and Enhanced Device Performance

In this letter, a double-spacer (DS) design is utilized for the formation of shallow source and lightly doped drain to further optimize the impact-ionization MOS (I-MOS) transistor structure. The breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> needed for avalanche breakdown is lowered due to the shallow source extension. With the formation of the lightly doped drain extension, the impact of drain bias on breakdown voltage, and hence, the threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> is also reduced. The DS I-MOS is fabricated and characterized. Detailed analysis and physical explanation of the impact of drain/gate bias on the device characteristics are provided. Compared to the conventional I-MOS transistor, the shallow source extension reduces the breakdown voltage [drain-induced breakdown voltage lowering (DIBVL)] by 0.3-0.6 V, and the lightly doped drain extension reduces the DIBVL up to 0.17 V/V. In addition, excellent subthreshold swing and good device performance are achieved.

Application of lightly doped drain structure to AlGaN/GaN HEMTs by ion implantation technique

AlGaN/GaN high electron mobility transistors (HEMTs) with lightly doped drain (LDD) structures were fabricated using an Si ion implantation technique. The HEMTs show an obvious merit of enhancement of on-state breakdown voltage (Vbr) of as high as 180 V, where that of a reference device without the LDD structure was 130 V. We also confirmed that resistance values at heavily doped drain regions were not changed by the introduction of the LDD structure.

테라비트급 나노 스케일 SONOS 플래시 메모리 제작 및 소자 특성 평가

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of , 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

Comparison of hot-hole injections in ultrashort channel LDD nMOSFETs with ultrathin oxide under an alternating stress

The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain (LDD) nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injections, i.e. low gate voltage hot hole injection (LGVHHI), gate-induced drain leakage induced hot-hole injection (GIDLIHHI) and substrate hot-hole injection (SHHI), have different influences on the devices damaged already by the previous hot electron injection (HEI) because of the different locations of trapping holes and interface states induced by the three types of injections, i.e. three types of stresses. Experimental results show that GIDLIHHI and LGVHHI cannot recover the degradation of electron trapping, but SHHI can. Although SHHI can recover the device's performance, the recovery is slight and reaches saturation quickly, which is suggested here to be attributed to the fact that trapped holes are too few and the equilibrium is reached between the trapping and releasing of holes which can be set up quickly in the ultrathin oxide.

Lateral Diffusion of Phosphorous Induced by Excimer Laser Irradiation of Silicon Thin Film for Formation of Gradual Lightly Doped Region in Polycrystalline Silicon Thin Film Transistors

A gradual lightly doped region was fabricated in a polycrystalline silicon (poly-Si) film by the lateral diffusion of dopants induced by excimer laser annealing. The lateral diffusion of phosphorous induced by excimer laser irradiation was verified, and the lateral diffusion length was measured by electrostatic force microscopy (EFM). The graded lateral diffusion profile was also observed by EFM. The lateral diffusion length from a heavily doped Si region to the intrinsic Si region was varied from 1.35 to 4.28 µm depending on the excimer laser energy density and irradiation number. The experimental results indicate that a lightly doped drain (LDD) structure can be fabricated in poly-Si thin film transistors (TFTs) by the lateral diffusion of dopants without the need for any additional mask.

Unified Subthreshold Model for Channel-Engineered Sub-100-nm Advanced MOSFET Structures

In this paper, a universal and computationally efficient subthreshold model for sub-100-nm nonuniformly doped channel MOSFET has been presented. The model incorporates drain-induced barrier lowering effect by means of the short-channel depletion width parameter d, which is evaluated using the voltage doping transformation method. The model can accurately predict the following: 1) surface potential; 2) electric field; 3) threshold voltage; and 4) subthreshold slope, for various lateral as well as transverse channel-engineered structures such as retrograde, graded channel, lightly doped drain (LDD), halo, and pocket implant technology for sub-100-nm channel length. In this paper, we have also proposed a novel device architecture incorporating the benefits of asymmetric halo and LDD doping. The analytical results have been verified by ATLAS 2-D device simulation software.

Halo and LDD Engineering for Multiple ${\rm V}_{\rm TH}$ High Performance Analog CMOS Devices

High performance analog (HPA) CMOS devices with multiple threshold voltages have been successfully fabricated in a 0.13-mum logic-based mixed-signal CMOS process on a single chip. The HPA devices demonstrate superior drivability, dc gain, matching, and reliability using an optimized halo and lightly doped drain (LLD) engineering approach combined with a unique dual gate oxide module for aggressive gate oxide thickness scaling.

On the reverse short‐channel effect and threshold voltage roll‐off controls for 90 nm node MOSFETs

In order to let device designers tune the short channel behavior of MOSFETs, a method is proposed in this work to demonstrate how to use LDD (lightly doped drain) and pocket implants to control RSCE (reverse short channel effect) and threshold voltage (Vt ) roll‐off. The method is based on the process parameters and silicon data of the 90 nm node technology of UMC (United Microelectronics Corporation). With the help of computers, 17 different process conditions of 8 different gate lengths were simulated using ISE TCAD to collect Vt variation data. Four characteristics representing the short channel behaviors of the MOSFETs were designed and extracted from the simulated data. Their empirical equations were also established subsequently. After verification, those mathematical models were demonstrated to help device designers in choosing the most suitable LDD and pocket implant parameters to generate required Vt characteristics.

Hot-Carrier Degradation and Electric Field and Electron Concentration near Drain Junction in Low-Temperature N-Channel Single Drain and Lightly Doped Drain Polycrystalline Silicon Thin Film Transistors

We proposed a two-dimensional (2-D) physical model of n-channel polycrystalline silicon (poly-Si) single drain (SD) and lightly-doped drain (LDD) thin film transistor (TFT) to analyze hot-carrier degradation. The model is based on a 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. It is found that, for current saturation bias, the maximum 2-D lateral electric field is located in the deep drain region under the gate, and the current flows in the deep channel region near the drain junction. In poly-Si n-channel TFTs, it was predicted from our 2-D device simulation that the generation of both band-tail states in poly-Si and interface states at both interfaces can contribute to hot-carrier degradation. We have shown that, in the case of n-channel SD TFTs, generated band-tail states greatly affect drain avalanche hot-carrier (DAHC) degradation for longer stress time of 10,000 s.

Hot-carrier degradation for 90 nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90 nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide under the low gate voltage (LGV) (at Vg = Vth, where Vth is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (Vg = Vth) stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Vg = Vth with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (~0.8).

Low temperature short channel polycrystalline silicon thin film transistors with high reliability for flat panel display

We have investigated a short channel ( L ≤ 1 μm) effect on the electrical reliability of the low temperature poly-Si thin film transistors (TFT) on a glass substrate. The threshold voltage of the p-type poly-Si TFT was observed to be decreased due to the drain induced barrier lowering as the channel length decreased. In the n-type poly-Si TFT with a lightly-doped-drain (LDD), the threshold voltage was slightly decreased when a high drain voltage was applied, while the field effect mobility decreased due to the series resistance of the LDD region in the short channel poly-Si TFT. As the temperature increased, the field effect mobility increased about 80% due to the increase of the thermal activated carrier concentration. We have also investigated the degradation of a short channel poly-Si TFT under hot carrier and self-heating stress. After hot carrier stress ( V GS = 2 V, V DS = 15 V), the field effect mobility was considerably decreased up to 20% due to the trap state generation induced by the hot carrier. The subthreshold slope and threshold voltage were scarcely degraded. After the self-heating stress ( V GS = V DS = 15 V), the subthreshold slope, mobility, and threshold voltage were degraded. Transfer characteristics measured at the high drain voltage ( V DS = 10 V) were shifted to a negative direction because of hole trapping at the backside interface between the polysilicon film and buffer oxide on the glass substrate.

Design of Ultra-High Performance Si TFTs

Design considerations for making use of ultra-high performance Si TFTs for future display systems are presented. Careful choice of the thickness and impurity concentration of the TFT channel is important to maximize the breakdown voltage. In the sub-micron regime, a lightly-doped-drain (LDD) structure is needed to suppress drain-induced phenomena. Layout design considerations based on the knowledge on the channel location dependence of device parameters and alignment method of TFT channels to the grain pattern are important to achieve high performance, while avoiding the undesirable effects of grain-boundary defects.

A Test Structure to Analyze Highly-Doped-Drain and Lightly-Doped-Drain in CMOSFET

A test structure to separately measure sheet resistances of highly-doped-drain (HDD) and lightly-doped-drain (LDD) in LDD-type CMOSFETs with various gate spaces S having sub-100 nm sidewalls was proposed. From the reciprocal of source/drain-resistance R -1 versus S characteristics, the sheet resistance ρ H of the high-conductive-region (HCR) corresponding to HDD and the approximate width W LC of the low-conductive-region (LCR) corresponding to LDD could be estimated. Both of ρ H and W LC for p- and n-MOS devices were scarcely dependent on the gate voltage. The sidewall-width difference of 40 nm could be sufficiently detected by using the test structure with the S pitch of about 60 nm. The R -1 versus S characteristics showed the unstable resistance variations in the narrow S region less than 0.3 μm, which corresponded to the minimum S for the process used for the test device fabrication and suggested that various micro-loading effects seriously affected on the characteristics.

Local resistance measurement across grain boundaries in low-temperature polycrystalline silicon layer of thin film transistor using scanning spreading resistance microscopy

Local resistance distribution in a low-temperature polycrystalline Si layer of a thin film transistor with a lightly doped drain (LDD) structure was investigated using scanning spreading resistance microscopy. The local resistance around the grain boundaries was found to be lower than that at grain insides in the drain, LDD, and channel regions. At the center of the grain boundaries, however, slightly higher resistance part was sandwiched between low resistance regions. Identifying the drain, the LDD, and the channel regions is succeeded by an analysis in which only the lower local resistances were used.

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.

HfC field emitter array controlled by built-in poly-Si thin film transistor

The HfC-coated Si field emitter arrays (FEAs) controlled by built-in poly-Si thin-film transistors (TFTs) were fabricated. The FEAs were fabricated at a relatively low temperature using Ar-ion-sputter sharpening so that a low-temperature poly-Si TFT process can be applied. A HfC thin film was coated on emitting tips for improving emission lifetime. An emission control TFT having a conventional top-gate structure was fabricated using ion implantation and activation annealing. A combination of multigate and lightly doped drain (LDD) structures was effective at reducing leakage current at a high source-drain voltage. We fabricated a HfC FEA integrated with a TFT having four gate electrodes with a LDD structure. Complete control of FEA emission current by built-in TFT was demonstrated in a vacuum chamber. The detailed fabrication process and emission control characteristics are reported.