Device Physics and Performance Optimization of Impact-Ionization Metal–Oxide–Semiconductor Transistors formed using a Double-Spacer Fabrication Process

Abstract

In this paper, the impact-ionization metal–oxide–semiconductor (I-MOS) transistor structure is further optimized by utilizing a double-spacer fabrication process. This novel fabrication process allows for performance optimization through independent tuning of four individual implants which form a shallow source region, a lightly-doped drain region, a heavily-doped drain region, and a deep source region. The performance optimization is guided by detailed understanding of the device physics and will be described. The breakdown voltage needed for avalanche breakdown is optimized using the shallow source extension, and the lightly-doped drain extension reduces the impact of drain bias on breakdown voltage and hence the threshold voltage. The heavily-doped drain and deep source implants reduce the parasitic series resistance of the transistor. The double-spacer I-MOS is fabricated and characterized. Detail analysis and physical explanation of the impact of drain/gate bias on the device characteristics will be given. In addition, excellent subthreshold swing and good device performance are achieved.