Parameter extraction of lightly-doped drain (LDD) MOSFETs

Abstract

Modern MOSFETs often incorporate a lightly-doped drain (LDD) region. Due to the presence of the LDD region, these so called LDD MOSFETs have a smaller electric field near the drain region and therefore a reduced hot-carrier effect over the conventional MOSFET [1, 2]. This, however, comes with the expenses of an increase in the drain/source series resistances and therefore a reduced drain current level. Figure 6.1 (a)-(c) give the schematic of the cross section of conventional MOSFET, LDD MOSFET, and fully overlapped LDD (FOLD) MOSFET, respectively. It can be seen that the LDD and FOLD MOSFETs differ mainly in the gate structure; the LDD MOSFET has a typical polysilicon gate surrounded by the oxide sidewall, whereas the FOLD MOSFET has a larger gate consisting of a polysilicon gate and two spacers. Let us focus on the LDD MOSFET. The lightly and heavily doped drain and source regions are fabricated as follows. First, the lightly-doped n drain and source regions are formed by ion implantation defined by the edges of the polysilicon gate. The heavily-doped n+ drain and source regions are then formed by a second ion implantation defined by the edges of the oxide sidewalls.