Lightly Doped Drain Structure Research Articles

6.4: The Effect of LDD Structure on the Characteristics of TFT Devices

Low temperature polycrystalline silicon thin film transistor (LTPS TFT) has a wide application prospect in flat panel display and other fields due to its higher carrier mobility and better conductivity. Motivated with the development of flat‐panel display devices targeting higher resolution, it is imperative to carry out research in small‐sized LTPS TFT technology. When the channel size is decreased to a certain extent, the effect of the gradual channel approximation is no longer valid. As a result, the short channel effect and the hot carrier effect will have significant impacts on the LTPS TFT devices. To alleviate and eventually to eliminate these two effects, we introduce and implement the Lightly Doped Drain (LDD) structure in the LTPS TFT device. LDD is a technology by adding lightly doped region between source and drain in a TFT, its series resistance is increased, thereby greatly reducing the electric field of drain, resulting in much less hot carrier effect and short channel effect. However, the introduction of LDD structure might have some adverse impacts on the characteristics of LTPS TFT if not optimized. In this paper, we studied the influence of different LDD structures on TFT performance, finding out the optimal LDD structure.

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

We lead the lightly doped drain (LDD) structure into the bridged‐grain (BG) poly‐Si thin film transistor (TFT). This combined structure can restrain the gate induced drain leakage current (GIDL) and the electrical characteristics shows not much sacrifice. A high Ion/Ioff current ratio 3.79×108 is achieved. Besides, the device reliability is improved significantly. Because the lateral electrical field decreases by LDD, lower trap state density is generated in the SiO2/poly‐Si interface and the grain boundaries of poly‐Si near the surface conduction channel, resulting in the stable on‐state drive current (Ion) and drain saturation voltage (Vdsat). All test results indicate that the BG poly‐Si TFT with a LDD structure will work well and has a great potential for system‐on‐panel application.

On-Current Decrease After Erasing Operation in the Nonvolatile Memory Device With LDD Structure

The on-current decrease phenomenon is observed after erasing operation in the silicon-oxide-nitride-oxide-silicon thin-film transistors (TFTs) with lightly doped drain (LDD) structure. As nonvolatile memory, when the TFT is programmed again, the on-current decrease phenomenon can be recovered. The on-current decrease and recovery are explained by the energy band diagrams at different drain biases. The explanation implies that this phenomenon only appears in the device with LDD structure, but not in the device without LDD structure, which is experimentally verified.

High Field Induced Stress Suppression of GIDL Effects in Accumulation-Mode P-Channel TFTs

By utilizing the effects of high energy, or "hot", electrons the GIDL current in an accumulation mode thin-film PFET can be suppressed. Both SOI and single crystal silicon-on-glass (SiOG) substrates were used to examine this effect. This suppression is proposed to be due to local injection of charge into the gate-oxide at the drain end of the transistor creating a mirror charge in the silicon which mimics an asymmetrical lightly-doped drain structure. An overview of theory, modeling, and device characterization is presented in this study. This effect has been shown to be stable and reproducible; a technique to measure the location and quantity of injected charge is under development.

LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide

We investigate planar fully depleted silicon-on-insulator(SOI) MOSFETs with a thin buried oxide (BOX) and a ground plane (GP). To study the depletion effects in the lightly doped drain (LDD) and substrate, we compare different BOX/GP/ LDD structure combinations. A novel GP back-gate engineering approach is introduced to improve both short-channel effects (SCEs) and LDD resistance. In this technique, an LDD/channel/ LDD mirror doping structure is reproduced in the back gate underneath the thin BOX. It is shown that SCEs are rather insensitive to SOI layer thickness variations and remain well controlled for gate lengths down to 15 nm for both nMOS and pMOS transistors due to outstanding electrostatic control: 63 mV/dec subthreshold swing and 7 mV/V drain-induced barrier lowering at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> = 1 V. The shift of the threshold voltage ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> with silicon film thickness Tsi down to 0.5 mV/nm is obtained. Simulations show that a 20% reduction in LDD resistance can be achieved in thin BOX devices with an optimized GP, as compared with thick BOX transistors. In addition, an improvement in drive current is also reported.

Mechanism Analysis of Off-Leakage Current in Poly-Si TFTs with LDD Structure

We have analyzed the mechanism of off-leakage current in a lightly doped drain (LDD) poly-Si thin film transistor (TFT) structure using a two-dimensional device simulation and by evaluating the temperature dependence. The off-leakage current in the self-aligned TFTs is mainly caused by band-to-band tunneling, and the off-leakage current in the LDD TFTs is mainly caused by phonon-assisted tunneling with the Poole-Frenkel effect. The carrier generation mostly occurs near the intersection of the front-insulator interface and the interface between the LDD and drain regions because both the electron and hole densities are simultaneously low and the electric field is strong.

The Channel Length Extension in Poly-Si TFTs With LDD Structure

In this letter, the resistance of the lightly doped drain (LDD) region in n-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) was analyzed. It was found that the LDD resistance was composed of an LDD-length-dependent part and a gate-bias-dominant part. The latter was located next to the gate edge and was governed by the channel extension phenomenon with an extended length of around 0.55 mum under a 10-V gate bias. The current density distribution simulated by Silvaco ATLAS supported this severe fringing field effect. The influences of the gate bias, LDD doping level, gate oxide thickness, and LDD length on the channel extension are also investigated with Silvaco ATLAS simulation. This letter is the first report of long channel extensions in the LDD region of poly-Si TFTs. The result may significantly influence the device model in the short channel regime.

Application of lightly doped drain structure to AlGaN/GaN HEMTs by ion implantation technique

AlGaN/GaN high electron mobility transistors (HEMTs) with lightly doped drain (LDD) structures were fabricated using an Si ion implantation technique. The HEMTs show an obvious merit of enhancement of on-state breakdown voltage (Vbr) of as high as 180 V, where that of a reference device without the LDD structure was 130 V. We also confirmed that resistance values at heavily doped drain regions were not changed by the introduction of the LDD structure.

HfC field emitter array controlled by built-in poly-Si thin film transistor

The HfC-coated Si field emitter arrays (FEAs) controlled by built-in poly-Si thin-film transistors (TFTs) were fabricated. The FEAs were fabricated at a relatively low temperature using Ar-ion-sputter sharpening so that a low-temperature poly-Si TFT process can be applied. A HfC thin film was coated on emitting tips for improving emission lifetime. An emission control TFT having a conventional top-gate structure was fabricated using ion implantation and activation annealing. A combination of multigate and lightly doped drain (LDD) structures was effective at reducing leakage current at a high source-drain voltage. We fabricated a HfC FEA integrated with a TFT having four gate electrodes with a LDD structure. Complete control of FEA emission current by built-in TFT was demonstrated in a vacuum chamber. The detailed fabrication process and emission control characteristics are reported.

Low-temperature metal-induced unilateral crystallized polycrystalline silicon thin-film transistor and gate-modulated lightly-doped drain structure

In this paper the low-temperature metal-induced unilaterally crystallized (MIUC ) polycrystalline silicon thin-film transistors (TFTs) have been developed and c haracterized. These TFTs have higher field-effect mobility, lower off-state curr ent and better spatial uniformity. A new structure of gate-modulated lightly dop ed drain of TFT was proposed. It is very effective to lower gate-induced drain-l eakage current of the TFTs when a higher source drain voltage is applied to it. This type MIUC TFT is suitable to fabricate active matrices for liquid crystal and organic light-emitting diode flat-panel displays on large area glass substr ates.

High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure

This investigation examines polycrystalline silicon thin-film transistors (TFTs) with multiple nanowire channels and a lightly doped drain (LDD). A device with an LDD structure exhibits low leakage current because the lateral electrical field is reduced in the drain offset region. Additionally, multiple nanowire channels can generate fewer defects in the polysilicon grain boundary and have more efficient NH3 plasma passivation than single-channel TFTs, further reducing leakage current. They exhibit superior electrical characteristics to those of single-channel TFTs, such as a higher ON/OFF current ratio (&amp;gt;108), a better subthreshold slope of 110 mV/decade, an absence of drain-induced barrier lowering, and suppressed kink-effect. Devices with the proposed TFTs are highly promising for use in active-matrix liquid-crystal display technologies.

A new self-consistent model for the analysis of hot-carrier induced degradation in lightly doped drain (LDD) and gate overlapped LDD polysilicon TFTs

Hot-carrier induced degradation is a main issue in the electrical stability of polysilicon TFTs and drain field relief architectures have been introduced, such as lightly doped drain (LDD) and gate overlapped LDD (GOLDD), to improve the stability. Bias-stress experiments were performed on both LDD and GOLDD structures, biasing the devices above pinch-off at constant V g and different V ds. While the LDD structure presented considerable hot-carrier induced degradation, GOLDD devices were characterised by a very high electrical stability. To explain such a difference in electrical stability, we first analysed the spatial distributions of the electric fields, which are lower in GOLDD structures. In addition, we developed a new model to describe the hot-carrier induced degradation, based on the correlation between hot carrier injection currents and interface state generation. Indeed, hot carrier injection is known to produce interface states and oxide trapped charge, and, depending upon their spatial distribution, can strongly influence the local electric fields as well as the current. The proposed model nicely reproduces the degraded characteristics, thus providing indications on the spatial distribution of the generated interface states.

Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOi NMOS devices with lightly-doped drain structure biased in strong inversion

This paper reports a closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted (FD) SOI NMOS devices with lightly-doped drain (LDD) structure. As verified by the two-dimensional (2-D) simulation results, the analytical drain current model considering energy transport and self-heating provides an accurate prediction of the drain current behavior of the 0.25-/spl mu/m FD SOI NMOS device with and without an LDD structure. From the analytical model, with the LDD structure, the device has a smaller effective electron mobility at a low drain voltage, where lattice temperature is dominant, and a higher effective mobility at a high drain voltage, where electron temperature dominates, as compared to the non-LDD device.

Improved lifetime of poly-Si TFTs with a self-aligned gate-overlapped LDD structure

We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H/sub 2/ ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation.

핫 캐리어 신뢰성 개선을 위한 새로운 LDD 구조에 대한 연구

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

Fabrication of Low-Temperature Poly-Si Thin Film Transistors with Self-Aligned Graded Lightly Doped Drain Structure

A novel approach for fabricating low-temperature poly-Si (LTPS) thin film transistors (TFTs) with self-aligned graded lightly doped drain (LDD) structure was demonstrated. The self-aligned graded LDD structure was formed by side-etching the Al gate under the photoresist followed by excimer laser irradiation for dopant activation and lateral diffusion. The graded LDD poly-Si TFTs exhibited low-leakage-current characteristics without significantly sacrificing driving capability due to the graded dopant distribution in the LDD regions, in which the drain electric field could be reduced. The leakage current of 1 μm graded LDD LTPS TFTs at Vds = 5 V and Vgs = -10 V could reach below 1 pA/μm, and the on/off current ratio at Vds = 5 V exceeded 10 7 .

A novel high performance stacked LDD RF LDMOSFET

A novel silicon RF lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) structure, using a simple yet effective concept of stacked lightly doped drain (LDD), is proposed. The stacked layers of LDD minimizes the on-state resistance of the transistor due to the n+ doping used in the top LDD layer, and also raises the device breakdown voltage due to the charge compensation in the composite LDD region. Therefore, for the same blocking voltage rating, the stacked LDD structure allows the LDMOSFET to have a higher current handling capability. This in turn causes the transconductance Gm to be higher, leading to higher RF performance for the power device. Measured results show that a 67% improvement in I/sub dsat/ and a 16% improvement in forward blocking voltage are obtained. Furthermore, the new device achieves an increase in transconductance of 145% and improves cut-off frequency by 108% at a gate voltage of 10 V.

Influence of the lightly doped drain resistance on the worst-case hot-carrier stress condition for NMOS devices

In this paper the underlying mechanisms that produce the cross-over in worst-case hot-carrier stress condition observed at room temperature in some deep submicron lightly doped drain (LDD) NMOS devices and at cryogenic temperatures for devices with longer channel lengths are investigated. Experiments were performed that demonstrate the generality of the cross-over. The role of stress temperature, measurement temperature and stress condition were experimentally addressed. The temperature dependence of the mobility was measured, and an analysis is presented that shows that mobility changes alone do not explain the observed changes in the transconductance. A model is proposed that allows for changes in the source–drain resistance with stress time. It is suggested that the origin of the time-dependent increasing source–drain resistance is the injection of charge, either in the form of fixed charge or as interface states, into the spacer oxide above the LDD region. This model is used to explain the qualitative dependence of the worst-case stress condition on channel length and temperature. Finally, it is suggested that the methodology used to design the LDD structure be modified to account for these new observations.

Extraction of the lightly doped drain concentration of fully depleted SOI NMOSFETs using the back gate bias effect

We present a simple method to extract the effective doping concentration related to the LDD (Lightly Doped Drain) regions in fully depleted SOI MOSFETs. The series resistance of an LDD structure MOSFET is composed of different components, the LDD series resistance, being the dominant one. The proposed method uses the back gate voltage influence on the back interface below the LDD region. MEDICI simulations were used to support the analysis. Experimental results obtained from I– V data were compared to the simulated results demonstrating a good agreement.

Photo-Leakage Current of Poly-Si Thin Film Transistors with Offset and Lightly Doped Drain Structure

The suppression of photo-leakage current (Iphoto) has been an important issue in the fabrication of high-brightness liquid-crystal projectors. We have investigated the generation mechanism of Iphoto in poly-Si thin film transistors (TFTs) with an offset structure. It is found that Iphoto is mainly generated at the offset region and the decrease in the offset length is important to suppress Iphoto. This is because the electric field is applied to the offset region and carriers, generated in the region, can be extracted. We have realized an offset poly-Si TFT with both high mobility and low Iphoto by decreasing the offset length to 0.5 µm with the lateral etching method.