Gate Library Research Articles

Library Impact Data Project: Looking for the Link between Library Usage and Student Attainment

The Library Impact Data Project was a six-month project funded by Jisc and managed by the University of Huddersfield to investigate this hypothesis: “There is a statistically significant correlation across a number of universities between library activity data and student attainment.” E-resources usage, library borrowing statistics, and library gate entries were measured against final degree award for 33,074 undergraduate students across eight U.K. universities. The research successfully demonstrated a statistically significant relationship between library resource use and level of degree result; however, any conclusions drawn are not indicators that library usage and student attainment have a causal relationship.

Considering nearest neighbor constraints of quantum circuits at the reversible circuit level

Since many underlying quantum algorithms include a Boolean component, synthesis of the respective circuits is often conducted by a two-stage procedure: First, a reversible circuit realizing the Boolean component is generated. Afterwards, this circuit is mapped into a respective quantum gate cascade. In addition, recent physical accomplishments have led to further issues to be considered, e.g. nearest neighbor constraints. However, due to the lack of proper metrics, these constraints usually have been addressed at the quantum circuit level only. In this paper, we present an approach that allows the consideration of nearest neighbor constraints already at the reversible circuit level. For this purpose, a recently introduced gate library is assumed for which a proper metric is proposed. By means of an optimization approach, the applicability of the proposed scheme is illustrated.

ACCURATE GATE DELAY EXTRACTION FOR TIMING ANALYSIS OF BODY-BIASED CIRCUITS

Static body biasing is a circuit technique in which bias voltage is selected from more than one available voltage after manufacturing. It allows circuits to be designed at more favorable process corners; but effective application requires gate delays to be available for the new process corners, without the expense of re-characterizing individual gates. We show that the new delay of a gate (when body bias is applied) can be extrapolated from its old delay without body bias together with old and new delays of a few reference gates. Output transition time, which is another component of gate timing model, is extrapolated in a similar manner. Experiments with an industrial 32-nm gate library show that the average error in the new gate delays is less than 4.3%.

Self-consistent quantum process tomography

Quantum process tomography is a necessary tool for verifying quantum gates and diagnosing faults in architectures and gate design. We show that the standard approach of process tomography is grossly inaccurate in the case where the states and measurement operators used to interrogate the system are generated by gates that have some systematic error, a situation all but unavoidable in any practical setting. These errors in tomography can not be fully corrected through oversampling or by performing a larger set of experiments. We present an alternative method for tomography to reconstruct an entire library of gates in a self-consistent manner. The essential ingredient is to define a likelihood function that assumes nothing about the gates used for preparation and measurement. In order to make the resulting optimization tractable we linearize about the target, a reasonable approximation when benchmarking a quantum computer as opposed to probing a black-box function.

GATE REPLACEMENT TECHNIQUE FOR REDUCING LEAKAGE CURRENT IN WALLACE TREE MULTIPLIER

Leakage power has become more significant in the power dissipation of today’s CMOS circuits. This affects the portable battery operated devices directly. The multipliers are the main key for designing an energy efficient processor, where the multiplier design decides the digital signal processors efficiency. In this study gate replacement technique is used to reduce the leakage power in 4×4 Wallace tree multiplier architecture which has been designed by using one bit full adders. This technique replaces the gate which is at worst leakage state by a library gate .In this technique the actual output logic state is maintained in active mode. The main objective of our study is to calculate leakage power in 4×4 Wallace tree multiplier by applied gate replacement technique and it is compared with 4×4 Wallace tree full adder multiplier. The proposed method reduces 43% of leakage power in 4×4 Wallace tree multiplier.

Logic Synthesis of Ternary Quantum Circuits with Minimal Qutrits

This paper investigates a universal approach of synthesizing arbitrary ternary logic circuits in quantum computation based on the truth table technology. It takes into account of the relationship of classical logic and quan-tum logic circuits. By adding inputs with constant value and garbage outputs, the classical non-reversible logic can be transformed into reversible logic. Combined with group theory, it provides an algorithm using the ternary Swap gate, ternary NOT gate and ternary Toffoli gate library. Simultaneously, the main result shows that the numbers of qutrits we use are minimal compared to other methods. We also illustrate with two examples to test our approach.

All optical digital logic gates library

On the run towards making a photonic processor, which uses the photons of visible light rather than electric current to perform digital computations we propose all optical digital logic gate library consisting of NOR, OR, AND, XOR, and two compound gates. These gates which are designed using semiconductor ring lasers (SRL) are analyzed and modeled by developing rate equations. This digital library can be used in any CAD tool developed to design integrated pho- tonics components. The phenomenon of injection locking is used for the realization of logic gates.

Development of Device for Preventing Reverse Going at Library Gate

Development of Device for Preventing Reverse Going at Library Gate

A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present, there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using the BSIM4 transistor model. To speed up the computation time and without compromising simulation accuracy (achieved through BSIM4), two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65 nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE.

PAID – A NOVEL FRAMEWORK FOR DESIGN AND SIMULATION OF ASYNCHRONOUS CIRCUITS

Contrary to the synchronous circuits, the asynchronous circuits operate with a mechanism of local synchronization (without clock signal). For many years, they showed their relevance with respect to the synchronous circuits thanks to their properties of robustness, low power, low noise and modularity. However, the lack of design methods and associated tools prevents them from being widely spread. This paper deals with a new design methodology for integrated asynchronous circuits and EDA tools. The suggested design method allows on one hand to model circuits in a highlevel language, and on the other hand to generate circuits using only elementary logical gates and Muller gates. This method was prototyped by the development of an EDA design tool for asynchronous circuits. The combination of design methodologies and supporting tools creates a design framework for asynchronous circuits, namely PAiD ("Project of Asynchronous Circuit Design"). This framework allows compilation and synthesis of circuits, described by high-level language ADL ("Asynchronous Description Language"), to generate asynchronous circuits. The result of the synthesizer is a functional netlist of the circuits. This netlist can be then mapped to a specific-technology gate library for asynchronous circuits. During the design process, the circuit can be tested through the simulation process in different levels of abstraction.

Optically implementable designs of reversible sequential devices

We have proposed some new designs of reversible sequential circuits using NCT gate library and compared them with the earlier proposals. It has been shown that the present proposals have lower gate complexities and lower number of garbage bits compared to the earlier proposals. We have addressed some conceptual issues related to the feedback and the choice of gate library. Further it is shown that the proposed quantum / reversible circuits can be implemented optically.

Hybrid-CV Modeling for Estimating the Variability in Dynamic Power

Process variations and its impact on design is of critical importance to address power management and optimization challenges for sub-90 nm CMOS designs, to achieve low power. This paper examines the role of process variations on variability of dynamic power of a circuit. A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in dynamic power of a digital circuit to variations in process parameters. The dynamic power of a 2-input NAND gate is extensively characterized by mixed-mode simulations to be used as a library element for 65 nm process. Also an analytical model for dynamic power variation at the gate level is developed in terms of the load capacitance variation data. The proposed methodology is demonstrated with a 4-bit A 4-bit Wallace tree multiplier circuit built using the NAND gate library. The variation in its dynamic power is characterized by an extensive Monte Carlo analysis. The statistical technique of Response Surface Methodology (RSM) using Design of Experiments (DOE) and the Least Squares Method (LSM) is adopted to obtain a hybrid model for dynamic power of NAND gate and then this methodology is extended to a generic technology library by proposing the hybrid model based on the device CV characterization data for computational simplicity. It has been demonstrated that the statistical design based on our hybrid models can result in considerable savings of upto 88 in the power budget estimation of low power CMOS designs with an error of less than 0.012 against worst case design. Significant reductions in uncertainty by at least 6x on a normalized basis against worst case design has been achieved. Copyright © 2008 American Scientific Publishers.

Nonconvex Gate Delay Modeling and Delay Optimization

Convex delay models like the Elmore model, the related Logical Effort model, posynomial, and generalized posynomial models have always been favored by researchers, as convexity has a priori guarantees of global optimum solutions. The accuracy of the model may be sacrificed in this quest to generate convex delay models. In this paper, we investigate the use of signomial delay modeling for area/delay optimization. We present a procedure to automatically generate signomial gate delay models by nonlinear least squares fitting. As opposed to posynomial models, signomial models achieve better fits to SPICE generated data. However, signomials are not convex in general. Nevertheless, we show via duality arguments that we obtain near optimum (within 1%) solutions. Our optimization considers beta-ratio constraints, minimum and maximum size constraints for n- and p-transistors, rise/fall delays, and edge rates. The gate sizes for the fastest delay solution for a 44000-cell design, using the IBM 130-nm process, can be achieved in about 16 min of CPU time on a PC, and the area-delay tradeoff curve for 21 points can be generated in about 2 h of CPU time. To the best of our knowledge, this is the first report of using a true signomial delay model and its application to optimum gate sizing. In addition, we give performance details for the automatic data fitting for an 11-function library of static CMOS gates.

Optimal synthesis of linear reversible circuits

In this paper we consider circuit synthesis for n-wire linear reversible circuits using the C-NOT gate library. These circuits are an important class of reversible circuits with applications to quantum computation. Previous algorithms, based on Gaussian elimination and LU-decomposition, yield circuits with O(n2) gates in the worst-case. However, an information theoretic bound suggests that it may be possible to reduce this to as few as O(n2/log n) gates. We give an algorithm that is optimal up to a multiplicative constant, and Θ(log n) times faster than previous methods. While our results are primarily asymptotic, simulation results show that even for relatively small n our algorithm is faster and yields smaller circuits than the standard method. The proposed algorithm has direct applications to the synthesis of stabilizer circuits, an important class of quantum circuits. Generically our algorithm can be interpreted as a matrix decomposition algorithm, yielding an asymptotically efficient decomposition of a binary matrix into a product of elementary matrices.

Optimal synthesis of linear reversible circuits

In this paper we consider circuit synthesis for $n$-wire linear reversible circuits using the C-NOT gate library. These circuits are an important class of reversible circuits with applications to quantum computation. Previous algorithms, based on Gaussian elimination and LU-decomposition, yield circuits with $O\left(n^2\right)$ gates in the worst-case. However, an information theoretic bound suggests that it may be possible to reduce this to as few as $O\left(n^2/\log\, n\right)$ gates.

Minimal universal library for [formula omitted] reversible circuits

Reversible logic plays an important role in quantum computing. Several papers have been recently published on universality of sets of reversible gates. However, a fundamental unsolved problem remains: “ what is the minimum set of gates that are universal for n - qubit circuits without ancillae bits”. We present a library of 2 gates which is sufficient to realize all reversible circuits of n variables. It is a minimal library of gates for binary reversible logic circuits. We also analyze the complexity of the syntheses.

Bi-Directional Synthesis of 4-Bit Reversible Circuits

Reversible circuits play an important role in quantum computing, which is one of the most promising emerging technologies. In this paper, we investigate the problem of optimally synthesizing 4-bit reversible circuits. We present an enhanced bi-directional synthesis approach. Owing to the exponential nature of the memory and run-time complexity, all existing methods can only perform four steps for the Controlled-Not gate NOT gate, and Peres gate library. Our novel method can achieve 12 steps. As a result, we augment the number of circuits that can optimally be synthesized by over 5 × 106 times. We synthesized 1000 random 4-bit reversible circuits. The statistical analysis result supports our estimation. The quantum cost of our result is also better than the quantum cost of other approaches. The promising experimental results demonstrate the effectiveness of our approach.

Parameterized Non-Gaussian Variational Gate Timing Analysis

As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to the gate and wire variability. Therefore, statistical timing analysis (denoted by sigmaTA) is becoming unavoidable. In this paper, two new approaches for doing variational gate TA for Gaussian and non-Gaussian sources of variation in parameterized sigmaTA are presented. To start, a variational RC-pi load is approximated by using a canonical first-order model. Next, an accurate variational gate TA (VGTA) technique, which accounts for variational RC-pi loads, variational input transitions, and a variation-aware gate library, is introduced. The proposed method relies on static effective-capacitance-calculation method and its variational form. Experimental results demonstrate that VGTA exhibits an average error of 4% for gate delay and output transition time with respect to the Monte Carlo simulation with 104 samples. Next, a more efficient VGTA [called Fast VGTA (F-VGTA)] based on a single-iteration variational effective capacitance calculation is presented. Experimental results show that F-VGTA achieves an average error of 7% for gate delay and output transition time with respect to the Monte Carlo simulation with 104 samples but with runtimes that are about two times faster than VGTA.

Books from Hardy's Max Gate Library

Books from Hardy's Max Gate Library

On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology

A generalized methodology for modeling the effects of process variations on circuit delay performance is proposed by directly relating the variations in process parameters to variations in delay metric of a digital circuit. The 2-input nand gate is used as a library element for 65 nm gate length technology, whose delay is extensively characterized by mixed-mode simulations. This information is then used in a general-purpose circuit simulator SEQUEL, by incorporating appropriate templates for the nand gate library. A 4-bit times 4-bit Wallace tree multiplier circuit, consisting of about 300 2-input nand gates, is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized by an extensive Monte Carlo analysis. To extend this methodology for a generic technology library with a variety of library elements, modeling of nand gate delays by response surface methodology (RSM), in terms of process parameters, is carried out using design of experiments (DOE). A simple piecewise quadratic model, based on the least squares method (LSM), is proposed for one-parameter variation to address significant cubic effects observed in the delay response function. Then, a hybrid model for gate delays is generated by superimposing the interaction terms of DOE-RSM model upon the quadratic model of one-parameter variation to address the generalized case of simultaneous variations in multiple process parameters. The proposed methodology has been demonstrated for nand gate library with 266 gates, and the simplicity and generality of the approach make it equally applicable to a large library of cells for both statistical timing analysis and statistical circuit simulation at the gate level