Hybrid-CV Modeling for Estimating the Variability in Dynamic Power

Abstract

Process variations and its impact on design is of critical importance to address power management and optimization challenges for sub-90 nm CMOS designs, to achieve low power. This paper examines the role of process variations on variability of dynamic power of a circuit. A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in dynamic power of a digital circuit to variations in process parameters. The dynamic power of a 2-input NAND gate is extensively characterized by mixed-mode simulations to be used as a library element for 65 nm process. Also an analytical model for dynamic power variation at the gate level is developed in terms of the load capacitance variation data. The proposed methodology is demonstrated with a 4-bit A 4-bit Wallace tree multiplier circuit built using the NAND gate library. The variation in its dynamic power is characterized by an extensive Monte Carlo analysis. The statistical technique of Response Surface Methodology (RSM) using Design of Experiments (DOE) and the Least Squares Method (LSM) is adopted to obtain a hybrid model for dynamic power of NAND gate and then this methodology is extended to a generic technology library by proposing the hybrid model based on the device CV characterization data for computational simplicity. It has been demonstrated that the statistical design based on our hybrid models can result in considerable savings of upto 88 in the power budget estimation of low power CMOS designs with an error of less than 0.012 against worst case design. Significant reductions in uncertainty by at least 6x on a normalized basis against worst case design has been achieved. Copyright © 2008 American Scientific Publishers.