Level-shifted Pulse Width Modulation Research Articles

Evaluation of level-shifted carrier PWM technique for neutral-point stabilisation of five-level DCMLI

The persistent issue with diode-clamped multilevel inverter is unbalance in DC-link capacitor voltages. These variations become predominant at load power factor near to unity. Evolved techniques exist to balance capacitor voltages for three-level inverter. But for the inverters above three level, the problem still persists. In this paper, a novel level-shifted carrier pulse width modulation technique is proposed. As per this technique, carriers are level shifted based on the difference in capacitor voltage and phase currents. This leads to variation in duty cycle of the switches and thereby adjusting the charging and discharging of capacitors to balance capacitor voltages. The proposed technique is mathematically modelled and verified for five-level inverter using MATLAB SIMULINK.

Evaluation of level-shifted carrier PWM technique for neutral-point stabilisation of five-level DCMLI

Evaluation of level-shifted carrier PWM technique for neutral-point stabilisation of five-level DCMLI

Theoretical and Experimental Comparison Between Phase-Shifted PWM and Level-Shifted PWM in a Modular Multilevel SDBC Inverter for Utility-Scale Photovoltaic Applications

This paper discusses and compares phase-shifted pulse-width modulation (PS-PWM) and level-shifted PWM (LS-PWM) in a modular multilevel single-delta bridge-cell (SDBC) inverter for utility-scale grid-tied photovoltaic applications. This three-phase SDBC inverter provides the capability of operating even under power-distribution imbalances not only among three clusters, but also among cascaded bridge cells in each cluster. The main focus of this research lies in analyzing the capability of operation under severe power-distribution imbalances and presenting power-balancing methods based on zero-sequence current injection, which result in an extended power-balancing capability. This paper highlights that LS-PWM is superior to PS-PWM in both power-balancing capability and harmonic performance at the ac side of the SDBC inverter when operating under power-distribution imbalances. Experimental results obtained from a three-phase 10-kW downscaled system show good agreement with those from the theoretical analysis.

Open-End Multilevel Six-Phase Machine Drive System With Five Three-Leg Converters

This paper proposes and investigates a multilevel ac six-phase motor drive. The system is composed of five isolated three-leg voltage source inverters feeding the open-end windings of an asymmetrical six-phase induction motor (SPIM), which is adequate to generate multilevel voltages for high-power systems with voltage rating restrictions. A simple space vector pulse-width modulation (PWM) based on three similar individual planes and its implementation by means of equivalent level-shifted PWM are presented. A space vector pattern with a high number of voltage vectors redundancies is obtained. These redundancies and the application sequence of the voltage vectors are selected to minimize the amount of changes in the switching states and to decrease the harmonic distortion of the generated voltages. The vector pattern of this optimal modulation is obtained by analyzing only one plane and applied in the same way to the three planes as if they were independent. The developed PWM techniques have low computational complexity and are suitable for low-cost hardware implementations. Simulation results are used to compare the proposed topology with a conventional configuration in terms of harmonic distortion and semiconductor losses. Experimental results demonstrate the feasibility of the proposed drive system.

Evaluating the capacity of power and energy balance for cascaded H‐bridge multilevel inverter using different PWM techniques

Among the different multilevel topologies for inverters, cascaded H-bridge multilevel topology has been a good solution for high-power medium-voltage applications because of its modularity structure, voltage balancing, separated DC sources, harmonics reduction, reliability and lower stresses on switching devices. The most widely used pulse width modulation (PWM) techniques for cascaded H-bridge multilevel inverter are known as phase shifted and level shifted. This study presents a comparison of power and energy distribution (inter-phase and inter-bridge power and energy) of three-phase cascaded H-bridge multilevel inverter for the phase-shifted and the level-shifted carrier PWM (phase disposition). A detailed comparison of different PWM techniques with reference to total harmonic distortion in the output voltages, both cases using a filter and without filter are presented also in this study. Simulation for 11-level cascaded H-bridge inverter is carried out in MATLAB/SIMULINK and simulation results are presented.

21-level 3-phase cascaded h-bridge multi-level inverter with different multi-carrier level shift pwm techniques and their thd analysis

21-level 3-phase cascaded h-bridge multi-level inverter with different multi-carrier level shift pwm techniques and their thd analysis

A Modified Level-Shifted PWM Strategy for Fault-Tolerant Cascaded Multilevel Inverters With Improved Power Distribution

To increase the fault tolerance for cascaded H-bridge multilevel inverters (CHMIs) based on level-shifted pulse width modulation (LS-PWM), a modified LS-PWM method is proposed for the inverters operating under faulty conditions. To cover both open- and short-device fault cases, two types of switching scheme are included in this PWM method. With this PWM method, the neutral shift can be applied as fault-tolerant control for CHMIs based on LS-PWM. Finally, three-phase-balanced line-to-line voltages and currents with minimum harmonic distortion are produced for the inverter with disabled power cells. In addition, this LS-PWM method has the capability to improve power distribution among the H-bridge power cells under the faulty conditions. Simulation and experimental results show that the proposed PWM method performs satisfactorily to achieve fault tolerance.

Self‐capacitor voltage balancing method for optimally hybrid modulated cascaded H‐bridge D‐STATCOM

A hybrid modulation (HM) for cascaded H-bridge converters is suggested which is a fusion of selective harmonic elimination (SHE) and carrier based bipolar pulse width modulation. It differs from its counterparts in the sense that only one triangular carrier for all H-bridges is used as opposed to multi-triangle waveform set and only one level of capacitor voltage and single type of semiconductor are considered. HM eliminates calculating and storing offline delay angles for each modulation index as in case of SHE. A novel self-voltage balancing mechanism is also proposed for HM which is based on strategically swapping redundant switching states. This mechanism is free from voltage sorting, current measurement, extra circuitry, or additional controllers. The comparison with phase and level shift pulse width modulation schemes reveal that the HM has 15% more DC voltage utilisation, and lower harmonic content for wide interval of modulation index. Moreover, HM has low semiconductor losses, as low as 0.55%. The tests on 1500 kVAR distribution static synchronous compensator shows that HM generates only 4% voltage ripple at the cost of few increase in average switching frequency. Voltage and reactive power balancing in each phase are also established with high power efficiency.

Analysis of Asymmetrical Cascaded Multi-Cell Multilevel Inverter Employing Multicarrier Level Shifting PWM Technique on Different Loads

Background: Multilevel inverters are very exciting alternative for intermediate and other high power drives. The Multicell group is widely growing owing to its advantages such as simplicity in circuit configuration with modularity and expandable. This paper proposes a new circuit configuration of 15 level cascaded H bridge Multicell Inverter which is the mixed form of flying capacitor and cascaded group. Methods: This work suggests a novel structure of new multilevel multicell inverter. The conventional structure uses two positive switch and two negative switch. Here the proposed inverter uses only one positive switch and only one negative switch. The circuit with one DC voltage along with one positive and negative switch forms a cell. Interconnection of more than one cells form multicell structure which is used to generate multilevel output. This multilevel inverter uses asymmetric voltage sources to produce multiple levels at the output. Here, Level Shifting Pulse Width Modulation (PWM) system is used to generate the switching signals to the inverter. Findings: The simulation of the proposed work shown with few number of semiconductor switches, is capable of achieving 15 levels at the output. Incorporating the Level Shifting PWM technique, the Total Harmonic Distortion (THD) has been reduced. Application: The proposed Multicell Multilevel inverter is used to drive the induction motor. Further controllers like PI, Fuzzy and Neuro can be added to reduce the THD and to develop the power quality.

Enervate carrier LS-PWM for reducing harmonic distortions in SCHB-MLI

Summary Among the different modulation techniques, pulse width modulation is one of the major renowned modulation strategies, because the pulses are generated based on reference signal and the reference signal is sinusoidal. Many modifications are made in this strategy since the PWM era starts in the area of power electronics; the modifications are related with the reference or carrier. This paper also discusses about the analysis with performance parameters when the carrier is modified with the impact of hysteresis band structures. The modified carrier is abridged towards the zero line of actual carrier; this type of carrier supports the reduction of the switching losses at the edge of pulse train and also reduces the total harmonic distortions from the converter output signal. The lower switching losses and better harmonic profile elevate the inverter performance; in this paper, Symmetrical Cascaded H-Bridge Multilevel Inverter is analysed with the proposed enervate carrier associated to level shift pulse width modulation.

VHDL Implementation of Capacitor Voltage Balancing Control with Level-Shifted PWM for Modular Multilevel Converter

Power electronics converters are a key component in high voltage direct current (HVDC) power transmission. The modular multilevel converter (MMC) is one of the latest topologies to be proposed for this application. An MMC generates multilevel output voltage waveforms which reduces the harmonics contents significantly. This paper presents a VHDL implementation of the capacitor voltage balancing control and level-shifted pulse width modulation (LSPWM) for MMC. The objective is to minimize the processing time with minimum gate counts. The design details are fully described and validated experimentally. An experiment is conducted on a small scale MMC prototype with two units of power cells on each arm. The test results are enclosed and discussed.

Detecting Open-Switch Faults: Using Asymmetric Zero-Voltage Switching States

This article presents a detection method for an open-switch fault in cascaded H-bridge multilevel inverters (CHMIs). Recently, CHMIs were widely used in high-power systems. Therefore, the reliability of this topology has become an important factor. To improve the reliability, methods for detecting openswitch faults are required. The proposed method is based on the current path analysis according to zero-voltage switching states. The location of both faulty cells and switches can be detected from the current waveform and zero-voltage switching states. This method is applicable when using the level-shifted pulsewidth modulation (LSPWM), which is commonly used for a modulation method in CHMIs. The performance of the proposed detection method is verified by simulation and experimental results.

CLPWM: Carrier Level Shifted Pulse Width Modulation based Multilevel Inverter Topology

In high-power medium-voltage applications requires multilevel inverters create a challenging task for industry and research. The conventional topologies are not sufficient to be a viable alternative for the above issues. This work achieves an active interest in the evolution of newer multilevel topologies using carrier level shifted modulation (CLPWM) for single level 27-levels. The primary objective of this work is to reduce the harmonics presents in the output voltage and current waveforms using proposed CLPWM technique. The proposed system consists of three H-bridge circuits based asymmetric topology using CLPWM to improve the conversion efficiency. The proposed asymmetric MLI provides 27 level step output for different DC voltage values. There is three H-bridge topology connected in the cascade arrangement for obtaining an AC voltage with 3n = 27 levels (n = 3 cascaded inverters). This method achieved by getting the proper switching angles using CLPWM generation for each H-bridge topology for medium voltage applications with low THD. Finally, our work investigates their suitability for single-phase 27-level multilevel inverter topology provides flat THD. A simulation model based on MATLAB/SIMULINK (version 2013) is developed.

Dynamic Voltage Restorer Based on Three-Phase Inverters Cascaded Through an Open-End Winding Transformer

This paper investigates a dynamic voltage restorer (DVR) composed of two conventional three-phase inverters series cascaded through an open-end winding (OEW) transformer, denominated here DVR-OEW. The DVR-OEW operating with either equal or different dc-link voltages is examined. The proposed topology aims to regulate the voltage at the load side in the case of voltage sags/swells, distortion, or unbalance at the grid voltage. A suitable control strategy is developed, including space-vector analysis, level-shifted PWM and its equivalent optimized single-carrier PWM, as well as the operating principles and characteristics of the DVR. Comparisons among the DVR-OEW and conventional configurations, including a neutral-point clamped converter-based DVR, are furnished. The main advantages of the DVR-OEW compared to the conventional topologies lie on: 1) reduced harmonic distortion, 2) reduced converter losses, and 3) reduced voltage rating of the power switches. Simulated and experimental results are presented to validate the theoretical studies.

A Novel Asymmetric Three-Phase Cascaded 21 Level Inverter Fed Induction Motor Using Multicarrier PWM with PI and Fuzzy Controller

Multilevel inverters are gaining popularity in high power applications. This paper proposes a new ladder type structure of cascaded three-phase multilevel inverter with reduced number of power semiconductor devices which is used to drive the induction motor. The ultimate aim of the paper is to produce multiple output levels with minimum number of semiconductor devices. This paper uses only 11 switches along with 3 diodes and 4 asymmetrical sources to produce an output voltage of 21 levels. The modulation technique plays a major role in commutation of the switches. Here we implement the multicarrier level shifting pulse width modulation technique to produce the commutation signals for the inverter. The proposed multilevel inverter is used to drive the three-phase induction motor. The mathematical modeling of three-phase induction motor is done using Simulink. Furthermore the PI and fuzzy logic controllers are also used to produce the reference waveform of the level shifting technique which in turn produces the commutation signals of the proposed multilevel converter. The controllers are used to control the speed of the induction motor. The effectiveness of the proposed system is proved with the help of simulation. The simulation is performed in MATLAB/Simulink. From the simulation results, it shows that the proposed multilevel inverter works properly to generate the multilevel output waveform with minimum number of semiconductor devices. The PI and fuzzy logic controller performances are evaluated using the results which indicate that with the help of controllers the harmonics has been reduced and the speed control of induction motor is achieved under different loading conditions.

Analysis and implementation of power management and control strategy for six-phase multilevel ac drive system in fault condition

This research article exploits the power management algorithm in post-fault conditions for a six-phase (quad) multilevel inverter. The drive circuit consists of four 2-level, three-phase voltage source inverter (VSI) supplying a six-phase open-end windings motor or/impedance load, with circumstantial failure of one VSI investigated. A simplified level-shifted pulse-width modulation (PWM) algorithm is developed to modulate each couple of three-phase VSI as 3-level output voltage generators in normal operation. The total power of the whole ac drive is shared equally among the four isolated DC sources. The developed post-fault algorithm is applied when there is a fault by one VSI and the load is fed from the remaining three healthy VSIs. In faulty conditions the multilevel outputs are reduced from 3-level to 2-level, but still the system propagates with degraded power. Numerical simulation modelling and experimental tests have been carried out with proposed post-fault control algorithm with three-phase open-end (asymmetrical induction motor/R-L impedance) load. A complete set of simulation and experimental results provided in this paper shows close agreement with the developed theoretical background.

Grid-connected Switched Reluctance Generator based Wind Farm Control using Modified Hybrid Multicell Converter

This study deals with analysis of grid integrated Switched Reluctance Generator (SRG) based wind farm control using Modified Hybrid Multicell Converter (MHMC). A Finite Element Analysis (FEA) model is developed for the existing machine geometry using MagNet 7.1.1 and solved to obtain the parameters like flux linkage, inductance and torque. The data obtained from FEA Model is utilized to develop model of SRG in the MATLAB/SIMULINK environment. Asymmetric Half Bridge Converter (AHBC) with dedicative buses for source and load is used for excitation. Developed wind turbine with Maximum Power Point Tracking (MPPT) algorithm to extract maximum power from the wind turbine. Output of the SRG is integrated with grid through Modified Hybrid Multicell Converter. The MHMC uses a flying capacitor module on each cell to generate a positive variable dc-link voltage. The variable dc link is inverted at fundamental switching frequency by an H-bridge to generate the cell output voltage. Phase-Disposition level-shifted Pulse Width Modulation (PD-PWM) Technique is used to obtain the high performance waveforms. In this study wind farm having four SRG’S controlled through MHMC is proposed.

English

Distribution Static Compensator (DSTATCOM) which based on multi-Level Cascaded H - bridge (CHB) Inverter for mitigation of harmonics and compensation of reactive power in Power System. This CHB based inverter provides low harmonic distortion, reduced number of switches and suppression of switching losses. It also helps to improve the power factor and eliminate the Total Harmonics Distortion (THD). Proportional and Integral (PI) control is used for capacitor dc voltage regulation. A level shifted PWM (LSPWM) technique is used to analyse the performance of CHB Inverter. A CHB Inverter is considered for shunt compensation of 11kV distribution system. The results are obtained through MATLAB & Simulink software.

Modular Multilevel Converter With an Adaptive Observer of Capacitor Voltages

A modular multilevel converter (MMC) is an attractive solution for power conversion without transformers. The MMC consists of cascade connections of floating dc capacitors. In this paper, an adaptive observer design has been proposed to estimate the capacitor voltages from the measurement of arm currents. This work introduces the capacitance value of the cell capacitors as a parameter uncertainty for making the system performance robust with unknown constant parameters. It may be used for predictive control, condition monitoring for capacitors, and diagnosis check for capacitor health. In addition, a pulsewidth modulation (PWM) technique for MMC has been explored. The PWM technique is performed using a carrier-based level-shifted PWM strategy. It does not necessitate the calculation of duty cycles, and can be easily implemented in a DSP. By using the PWM technique, harmonics in the phase voltage is shifted to twice the switching frequency. Theoretical analysis is included in this paper for showing stability and convergence of the proposed observer. Analytical expressions are verified by simulation and experimental results.

Novel carrier‐based hybrid pulse width modulation method for cascaded capacitor‐clamp multilevel inverter

This study presents a new carrier-based hybrid pulse width modulation (PWM) Method for the cascaded capacitor-clamp multilevel inverter (CCCMLI), which combines the benefits of a new alternative level-shifted carrier PWM and a phase-shifted carrier PWM. For modulating the CCCMLI, the phase disposition sub-harmonic PWM was first proposed, but does not show good performances in an even load sharing between inverter cells connected in series, flying-capacitor voltage balancing and output waveform quality. On the other hand, a proposed PWM method enables to achieve a balanced load sharing between cascaded cells even at low amplitude modulation indices as well as the excellent voltage balancing control of the flying-capacitors with a much smaller voltage ripple and the good harmonic characteristics in output waveforms. The proposed modulation is verified through both simulation and field-programmable gate array (FPGA) based experimental results.