CLPWM: Carrier Level Shifted Pulse Width Modulation based Multilevel Inverter Topology

Abstract

In high-power medium-voltage applications requires multilevel inverters create a challenging task for industry and research. The conventional topologies are not sufficient to be a viable alternative for the above issues. This work achieves an active interest in the evolution of newer multilevel topologies using carrier level shifted modulation (CLPWM) for single level 27-levels. The primary objective of this work is to reduce the harmonics presents in the output voltage and current waveforms using proposed CLPWM technique. The proposed system consists of three H-bridge circuits based asymmetric topology using CLPWM to improve the conversion efficiency. The proposed asymmetric MLI provides 27 level step output for different DC voltage values. There is three H-bridge topology connected in the cascade arrangement for obtaining an AC voltage with 3n = 27 levels (n = 3 cascaded inverters). This method achieved by getting the proper switching angles using CLPWM generation for each H-bridge topology for medium voltage applications with low THD. Finally, our work investigates their suitability for single-phase 27-level multilevel inverter topology provides flat THD. A simulation model based on MATLAB/SIMULINK (version 2013) is developed.