Leadless Ceramic Chip Carriers Research Articles

Analysis of the Thermally Induced Packaging Effects on the Frequency Drift of Micro-Electromechanical System Resonant Accelerometer.

Due to the working principle of MEMS resonant accelerometers, their thermally induced frequency drift is an inevitable practical issue for their extensive application. This paper is focused on reducing the thermally induced packaging effects on the frequency drift. A leadless ceramic chip carrier package with a stress-buffering layer was proposed for a MEMS resonant accelerometer, and the influences of packaging structure parameters on the frequency drift were investigated through finite element simulations and verified experimentally. Because of the thermal mismatch between dissimilar materials, the thermo-mechanical stress within the resonant beam leads to a change in the effective stiffness and causes the frequency drift to decrease linearly with increasing temperature. Furthermore, our investigations reveal that increasing the stress-buffering layer thickness and reducing the solder layer thickness can significantly minimize the thermo-mechanical stress within the resonant beam. As the neutral plane approaches the horizontal symmetry plane of the resonant beam when optimizing the packaging structure, the effects of the compressive and tensile stresses on the effective stiffness of the resonant beam will cancel each other out, which can dramatically reduce the frequency drift. These findings provide guidelines for packaging design through which to improve the temperature stability of MEMS resonant accelerometers.

Thermal fatigue reliability improvement of leadless ceramic chip carrier solder joints

In order to improve the thermal fatigue reliability of LCCC (Leadless Ceramic Chip Carrier) solder joints, the assembly process and failure mechanism of LCCC devices are analyzed. It is concluded that the solder joints height is the main factor to improve its thermal fatigue reliability. Reliability qualification tests are performed to contrast the improvement effect of several methods. The Sn10Pb90 column mounting specimen can greatly improve the fatigue reliability and can adapt to most environmental requirements. Some significant conclusions are drawn by comparing the tests results of different specimens. The method can also be used for the other package types to improve the reliability.

An Ultrahigh Vacuum Packaging Process Demonstrating Over 2 Million Q-Factor in MEMS Vibratory Gyroscopes

Micro resonators and vibratory gyroscopes could reach their fundamental thermo-elastic damping (TED) limit in an ultravacuum condition where the viscous damping is eliminated. This article presents a reliable and repeatable high vacuum sealing process as a standalone approach for performance evaluation of dynamic micro devices. We demonstrated a micro-Torr vacuum level in a ceramic leadless chip carrier package and achieved the Q-factor over 2million on a quad mass gyroscope, approaching the TED limit of the device by effectively eliminating the viscous damping. The long-term vacuum stability was characterized over 1 year and demonstrated that the Q-factor does not degrade over time and even continues improving. The long-term ultrahigh vacuum condition is enabled by surface desorption prior to sealing, pumping of residual gases by passive getters, and defect-free solder reflow in the sealing area. The experimental results confirmed the reliability and repeatability of the proposed sealing procedure, which can be adapted for other Micro Electro-Mechanical Systems (MEMS) with ultrahigh vacuum requirements.

Strain-Range-Based Solder Life Predictions Under Temperature Cycling With Varying Amplitude and Mean

To investigate modeling approaches for predicting solder interconnect fatigue life under field thermal conditions, a complex temperature cycle composed of three temperature dwell points was modeled and physically tested. Modeling the solder interconnect life expectancy under these complex conditions is accomplished by segmenting the complex temperature cycle into multiple simple temperature cycles, predicting the life expectancy of the solder interconnect under the simple temperature cycles using the Engelmaier model, and applying Miner's rule to superpose the damage of the segmented cycles and predict solder interconnect fatigue life under the complex temperature cycle. Several modeling strategies based on different segmenting schemes are presented, and the one with the best comparison with the physical test results is identified. A case study is presented for ceramic leadless chip carriers assembled with Sn62Pb36Ag2, Sn96.5Ag3Cu0.5, and SN100C solders. The Engelmaier model constants to model the simple temperature cycles are also provided as a basis for modeling the complex cycle.

A compact UHV package for microfabricated ion-trap arrays with direct electronic air-side access

We have demonstrated a new apparatus for operating microfabricated ion-trap arrays in a compact ultra-high-vacuum setup with excellent optical and electrical access. The approach uses conventional components, materials and techniques in a unique fashion. The microtrap chip is mounted on a modified ceramic leadless chip carrier, the conductors of which serve as the vacuum feedthrough. The chip carrier is indium-sealed to stainless-steel components to form vacuum seals, resulting in short electrical path lengths of ≤20 mm from the trap electrodes under vacuum to air side. The feedthrough contains conductors for the radio-frequency trap drive, as well as 42 conductors for DC electrodes. Vacuum pressures of ∼1 × 10−11 mbar are achieved, and ions have been confined and laser cooled in a microtrap chip. The apparatus enables accurate measurements of radio-frequency voltage amplitudes on the trap electrodes, yielding an excellent agreement between measured and modelled trap efficiencies. This feature is of significant use in establishing initial operation of new devices. The principle of the connectivity scheme presented here is applicable to larger ceramic chip carriers containing many more conductors.

Analysis of the Electronic Assembly Repair Process for Lead-Free Parts Under Combined Loading Conditions

The conversion from tin-lead (SnPb) to lead-free electronics has created concern amongst engineers about the reliability of electronic assemblies and the ramifications that reliability changes may have on the life-cycle cost and availability of critical systems that use lead-free electronics. In this paper, the impact of lead-free solder on the repair of electronic assemblies subject to combined thermal and vibration loading is studied. The cost, repair time, and availability of boards are quantified using a previously developed repair simulator for a test board developed and tested by the Joint Council on Aging Aircraft & Joint Council on Pollution Prevention that includes ceramic leadless chip carrier, thin small outline package, and plastic ball grid array packaged parts using SnPb and lead-free solders. This paper describes the process of calibrating a physics-of-failure reliability simulator using experimental highly accelerated life testing test results for a specific board assembly and using the calibrated model to generate failure distributions corresponding to combined thermal and vibration loading over an actual product life cycle for use in the repair simulator. The results of the repair simulation indicate that longer dwell times appear to cause more damage than larger Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> ; under combined loading conditions, SnPb appears to be more reliable than tin-silver-copper (for the board and parts considered in this paper) and as a result, repair cost is lower; and the number of failures and repair times track repair costs (depending on the capacity of repair process).

Vibration Durability of Sn3.0Ag0.5Cu (SAC305) Solder Interconnects: Harmonic and Random Excitation

In this study, the durability of lead (Pb)-free tin(Sn3.0)silver(Ag0.5)copper(Cu) (SAC305) printed wiring assemblies (PWAs) is investigated under constant amplitude, narrow-band (harmonic) excitation and under step-stress broad-band (random) excitation, and compared to the durability of Pb-based Sn37Pb PWAs. The results show that Sn37Pb assemblies last longer than SAC305 assemblies at similar excitation levels, for both harmonic and random excitations used in this study. The test specimens are identical for all tests, consisting of a PWA with plastic ball grid array components, quad flat pack components, leadless ceramic chip carriers, and leadless chip resistors. The test matrix includes test boards with different kinds of finishes and different aging conditions. Both the harmonic and random vibration tests are conducted on single-axis electrodynamic shakers. The harmonic vibration excitation is applied to a single specimen at a time, while the random vibration excitation is applied simultaneously to 20 test specimens using a specially designed test fixture. The flexural response of each test specimen mounted in the fixture is first thoroughly characterized before conducting the durability experiment. The flexural strain histories, measured on the PWAs, are used to compare the performance of the assemblies at different excitation conditions and also as inputs in other studies for stress analysis to quantify the damage in the solder joints.1 The durability tests are then conducted and time-to-failure is documented for the entire test matrix. The random durability tests are conducted at three temperatures: 125 °Centigrade (C), 25 °C (room temperature), and -40 °C. The harmonic tests are conducted only at room temperature. Destructive failure analysis (cross-sectioning, polishing, and microscopy) is conducted to confirm the failure modes. The test results presented here are analyzed in related publications1 to extract the high-cycle fatigue properties of the SAC305 and Sn37Pb solder materials.

A 9-bit Quadrature Direct Digital Synthesizer Implemented in 0.18-$\mu{\hbox {m}}$ SiGe BiCMOS Technology

This paper describes a 9-bit 6.2-GHz low power quadrature direct digital synthesizer (DDS) implemented in a 0.18-mum SiGe BiCMOS technology. With a 9-bit pipeline accumulator and two 8-bit sine-weighted current steering DACs, this DDS is capable of generating quadrature sinusoidal waveforms up to 3.15 GHz with a maximum clock frequency of 6.2 GHz. Packed with more than 13 500 transistors, the quadrature DDS occupies an active area of 2.3 times 2.5 mm2 and a total die area of 3.0 times 3.0 mm2. The measured spurious-free dynamic range is approximately 26 dBc at a clock frequency 6.2 GHz. At the maximum clock frequency, the power consumption of the DDS is 2.5 W with 3.3- and 4.0-V power supplies for the digital and analog parts, respectively. The DDS thus achieves a power efficiency figure-of-merit of 5.04 GHz/W/phase. The DDS chips were packaged with 48-pin ceramic leadless chip carriers and air cooling was used during the measurement.

Strain range fatigue life assessment of lead‐free solder interconnects subject to temperature cycle loading

PurposeThe aim is to present temperature fatigue model constants for lead‐free tin‐silver‐copper solder derived from test data and demonstrate the validity of the model using published experimental results.Design/methodology/approachTemperature cycle fatigue life data were collected from a controlled set of tests using ceramic leadless chip carriers. Using a regression algorithm, temperature cycle fatigue model constants were derived from fatigue life data. The model was then applied to a variety of package formats including ball grid arrays, quad flatpack and thin small outline packages to determine the validity of the model and constants.FindingsThe temperature cycle fatigue life experimental data were found to be in good agreement with the model with the derived model constants for various package types. Using this model, engineers can determine acceleration factors between test and field temperature cycle conditions.Research limitations/implicationsThe technology has been used to ensure inner layer designs with nominal dimensions after the lamination stage. Further, development work should be undertaken to collate measured data from other parts of the PCB manufacturing process and model the material movement around all registration critical processes.Originality/valueThe paper details a temperature cycle fatigue life model and constants that allow engineers to predict field life expectancy and determine the acceleration factor between temperature cycle testing and field use conditions.

Application of the Mixed‐field‐environments concept in lifetime prediction of some ceramic components

AbstractIn lifetime prediction, the effect of a certain use environment on the lifetime is taken into account by using an acceleration factor that is specific to that use environment. The fact that the product may be used in different countries with differing environmental conditions results in a set of acceleration factor values. Prior to this paper, the effect of multiple field environments has been taken into account by using an average value of the acceleration factors obtained for several use environments. As the magnitudes of the acceleration factors (each specific to a certain use environment) vary a lot, the use of the average value has resulted in unrealistic lifetime estimates. The unrealism related to the use of the average value can be avoided when using the mixture‐of‐distributions concept, since the true acceleration factor values, instead of an average value, can then be used. In this paper, the mixture‐of‐distributions concept is applied for the first time to evaluate the effect of multiple use environments (thermal cycling) on the lifetime of a component population. By using this concept, it is possible to evaluate all of the key figures of reliability for the whole population based on the fractions of the component population that are used in multiple, different use environments. This approach can be applied when allocating maintenance and spare parts for a product that is used worldwide. The mixture‐of‐distributions concept in lifetime prediction is demonstrated by analyzing the test results of some ceramic leadless chip carrier components. Acceleration factors in four alternative field environments are estimated by running thermo‐mechanical finite element analysis simulations. The lifetime performance of the whole component population used in certain alternative field environments is then evaluated by applying the mixture‐of‐distributions concept. Copyright © 2006 John Wiley &amp; Sons, Ltd.

A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS

An 8-PAM CMOS transceiver is described in this paper. Pre-emphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The prototype transmits at up to 1.3 Gb/s and has a measured bit error rate of less than 1 in 10/sup 13/ for an 810-Mb/s pseudorandom bit sequence transmission. The device, packaged in a 68-pin ceramic leadless chip carrier, is implemented in 0.5-/spl mu/m digital CMOS, occupies 2 mm/sup 2/, and dissipates 400 mW from a 3.3-V supply.

Integrated Thermal Analysis of Natural Convection Air Cooled Electronic Enclosure

In the present paper, a methodology is described for the integrated thermal analysis of a laminar natural convection air cooled nonventilated electronic system. This approach is illustrated by modeling an enclosure with electronic components of different sizes mounted on a printed wiring board. First, a global model for the entire enclosure was developed using a finite volume computational fluid dynamics/heat transfer (CFD/CHT) approach on a coarse grid. Thermal information from the global model, in the form of board and component surface temperatures, local heat transfer coefficients and reference temperatures, and heat fluxes, was extracted. These quantities were interpolated on a finer grid using bilinear interpolation and further employed in board and component level thermal analyses as various boundary condition combinations. Thus, thermal analyses at all levels were connected. The component investigated is a leadless ceramic chip carrier (LCCC). The integrated analysis approach was validated by comparing the results for a LCCC package with those obtained from detailed system level thermal analysis for the same package. Two preferred boundary condition combinations are suggested for component level thermal analysis.

Analytical and Experimental Hybrid Study on Thermal Fatigue Strength of Electronic Solder Joints. 1st Report. Rationalization of Accelerated Thermal Cyclic Test and Evaluation of Thermal Fatigue.

Stress-strain analyses for Sn-Pb cutectic solder joints in a thin single outline package (STOP), a ball grid array (BGA) assembly, and a leadless ceramic chip carrier (LCCC) were carried out for investigation of plastic-creep behavior, and of stress relaxation behavior due to accelerated thermal cycling tests or the operating conditions. the temperature dependence of plastic behavior (yield stress) and creep behavior (creep properties) were taken into account in all numerical analyses. The results of finite element analysis (FEA) show that in an accelerated terperature cycling test, long high-temperature and low-temperature dweel times do not contribute to an increase in the cyclic inelastic equivalent strain range in solder joints, although the creep behavior occurring during the dwell times under operating conditions is very important in estimation of the fatigue life of solder joints. Based upon the results of the strain analyses, an efficient temperature cycling test process for microelectronic solder joints was proposed, and cycling tests were carried out. The experimental results show that the thermal fatigue life of microelectronic Sn-Pb eutectic solder joints can be predicted by an associated fracture parameter of total equivalent inelastic strain range, and the fatigue life of solder joints follows Coffin-Manson's law.

Thermomechanical analysis in electronic packaging with unified constitutive model for materials and joints

A unified constitutive modeling approach based on the disturbed state concept (DSC) provides improved characterization of thermomechanical response of joining (solders), ceramics and printed wire board (PWB) materials in electronic packaging. Various versions in the DSC approach are calibrated and validated with respect to laboratory test data, and are implemented in a nonlinear finite element (FE) procedure. The hierarchical nature of this procedure permits the user to choose a constitutive model, simple (elastic) to sophisticated (elastovisco-plastic with disturbance), depending upon the material and need. The FE is used to analyze thermomechanical behavior of two typical problems: (1) leadless ceramic chip carrier (LCCC) package; (2) solder ball connect (SBC) package. The FE results under cyclic thermal loading are compared with experimental data for the two packages, and with a previous FE analysis for the SBC package. In conjunction with the idea of critical disturbance at which thermal fatigue failure can occur, the analyzes allow identification of cycles to failure, N/sub f/, and evaluation of reliability of the package. In the case of the SBC package, the analysis permits an evaluation of ball spacing on the thermomechanical behavior. The DSC approach can provide an integrated and improved procedure compared to available models for elastic, plastic, creep strains, and microcracking leading to degradation of strength and fatigue failure for a wide range of problems in electronic packaging under thermomechanical loading.

Characterizing the Commercial Avionics Thermal Environment for Field Reliability Assessment

Defining environmental loading is often the most uncertain part of the electronics reliability calculation. This paper demonstrates a practical methodology to measure and characterize the dynamic thermal history of the commercial airplane environment. To reduce irregular field thermal cycles, an algorithm is presented that preserves key information necessary for viscoplastic solder fatigue analysis. As an example. the IPC solder model will be used to evaluate 20 termination leadless ceramic chip carriers on nonconstrained printed wiring boards. This methodology will enable more realistic thermal fatigue reliability assessments and acceleration test specifications.

Fatigue-strength prediction of microelectronics solder joints under thermal cyclic loading

The stress-strain analyses for the solder joints in a thin single outline package (TSOP), a ball grid array (BGA) assembly, and a leadless ceramic chip carrier (LCCC) are carried out to investigate the plastic-creep behavior, and stress relaxation behavior due to the temperature cycling or isothermal cyclic loading. The temperature dependence of plastic behavior (yield stress) and creep behavior (creep properties) are taken into consideration in all numerical analyses. The results of finite element analysis (FEA) show that in an accelerated temperature cycling test, long high-temperature and low-temperature dwell times do not contribute to the increase of the cyclic inelastic equivalent strain range in solder joints (although the creep behavior occurring during the dwell times in an operating condition is important enough to be taken into consideration for estimating the fatigue life of solder joints). Based upon the results of the strain analyses, some efficient testing processes of temperature cycling and isothermal fatigue tests for the microelectronic solder joints are proposed, and the cycling tests are carried out. The experimental results show a good agreement with the analytic results.

Effect of intermetallic compounds on the thermal fatigue of surface mount solder joints

The effect of Cu-Sn intermetallic compounds (IMC) on the fatigue failure of solder joints during thermal cycling has been studied. The samples consist of components [leadless ceramic chip carrier (LCCC)] soldered onto FR-4 printed circuit board (PCB), and are prepared by conventional reflow soldering using a 63Sn-37Pb solder paste. The specimens are subjected to thermal cycling between -35/spl deg/C and 125/spl deg/C with a frequency of two cycles per hour until failure. The results indicate that the fatigue lifetime of the solder joints depends on the thickness of IMC's layer between Cu-pad and bulk solder, and the relation of the lifetime to the thickness can be described as a monotonically decreasing curve. The lifetime is very sensitive to the thickness of the IMC when the thickness is less than 1.4 /spl mu/m. During thermal cycling the thickness of the IMC layer increases and then the interface between IMC and solder becomes gradually flatter. The results of X-ray diffraction and scanning electron microscope (SEM) analysis show that cracks propagate along the interface between the IMC layer and the solder joint. The Cu/sub 3/Sn (/spl epsiv/-phase) is also found to form between the Cu-pad and /spl eta/-phase during thermal cycling. On the basis of the above results, the thick and flattened IMC layer is shown to responsible for the fatigue failure of solder joint during thermal cycling. The results of this paper can be used to optimize the reflow soldering process for the fabrication of robust solder joints.

Effect of intermetallic compounds on the shear fatigue of Cu/63Sn-37Pb solder joints

The effect of Cu-Sn intermetallic compounds (IMC) on the fatigue failure of solder joints has been studied by means of shear cycling. The samples consist of leadless ceramic chip carriers (LCCC) soldered onto FR-4 printed circuit boards (PCB), and are prepared by conventional reflow soldering using a 63Sn-37Pb solder paste and then aged at 150/spl deg/C for 1, 4, 9, 16, 25, 36, and 49 days. The specimens are subjected to low cycle fatigue shear tests controlled by the displacement. The results indicate that the fatigue lifetime of the solder joints depends on the thickness of the LMC layer between the Cu-pad and bulk solder, and the quantitative relationship between the lifetime and thickness can be described as a monotonically decreasing curve. The greatest decrease is over the thickness range up to 2.8 /spl mu/m, when the IMC/bulk solder interface becomes flat, corresponding to a lifetime decrease to 62% of the as assembled value. For further increase in IMC thickness the lifetime decreases more slowly. Evidently, the effect of the Cu-Sn intermetallic compounds on the joint fatigue lifetime is not only concerned with the IMC thickness hut also the interface morphology. A thick and flat LMC layer has a deleterious effect. The results of X-ray diffraction and metallographic analysis show that cracks initiate underneath the component metallization, and propagate along the IMC/solder interface, then toward the fillet. The Cu/sub 3/Sn (/spl epsiv/-phase) is formed between the Cu-pad and p-phase, and grows more quickly than the /spl eta/-phase during storage and long term operation or aging tests. However, the Cu/sub 3/Sn makes only a small direct contribution toward fatigue failure.

Finite element simulation of the temperature cycling tests

Temperature cycling tests are commonly used in the semiconductor industry to determine the number of cycles to failure and to predict reliability of the solder joints in the surface mount technology packages. In this paper, the thermomechanical fatigue of Pb40/Sn60 solder joint in a leadless ceramic chip carrier package is studied and temperature cycling test is simulated by using a finite element procedure with the disturbed state concept (DSC) constitutive models. The progress of disturbance (damage) and the energy dissipated in the solder joint during thermal cycling are predicted. It is shown that the disturbance criterion used follows a similar path as the energy dissipation in the system. Moreover, the comparisons between the test data and the finite element analysis show that a finite element procedure using the DSC material models can be instrumental in reliability analysis and to predict the number of cycles to failure of a solder joint. Furthermore, the analysis gives a good picture of the progress of the failure mechanism and the disturbance in the solder joint.

Controlled Thermal Expansion Printed Wiring Boards based on Liquid Crystal Polymer Dielecrics

L iguid crystal polymer (LCP) dielectric materials have been used to fabricate surface mount PWBs with a coefficient of thermal expansion matched to leadless ceramic chip carriers. Proprietary and patented polymer processing technology results in self‐reinforcing material with balanced in‐plane mechanical properties. In addition, LCPs possess excellent electrical properties, including a low dielectric constant (∼3) and very low moisture absorption (&lt; 0.02 %). Laser drilling of blind vias in the LCP dielectric provides a very high density for use in direct chip attach and area array packages. Modelling indicates that the high out‐of‐plane CTE of LCPs does not affect the reliability of the plated‐through‐holes vias. RF characterisation indicates that the material is suitable up to very high frequencies. The material is ideally suited to MCM‐L and PCMCIA applications involving very thin dielectric layers of the LCP.