LDPC Encoder Research Articles

Design and implementation of an LDPC encoder for satellite navigation system

Design and implementation of an LDPC encoder for satellite navigation system

Flexible and High-Efficiency LDPC Encoder Architecture for CCSDS Standard

Abstract The Consultative Committee for Space Data Systems (CCSDS) has adopted quasi-cyclic low-density parity-check (QC-LDPC) codes for use in near-Earth (C2) and deep space (AR4JA) communications. Existing encoder architectures for C2 codes, however, fall short in efficiency for high-throughput applications. This paper introduces a comprehensive approach combining algorithmic and architectural optimizations to enhance hardware usage efficiency (HUE) while offering flexibility. We propose an integrated inter-block and intra-block parallel (IIB-IBP) encoding algorithm that leverages the unique matrix structure to significantly enhance performance. Additionally, a matrix-specific command register pretreatment (MSCRP) technique is developed to effectively handle the special dimensions of the generator matrix. Furthermore, we detail an offline design process for the automated generation of the encoder core’s HDL description, facilitating fine-tuning of encoding parallelism, latency, FPGA resource utilization, and overall throughput. Hardware implementation on a Virtex XC5VLX110T FPGA demonstrates that our encoder reaches an impressive throughput of 10.6 Gb/s with only 2531 LUTs and 1040 FFs, achieving a HUE of 2.97 Mbps/logic unit. This performance marks a 70.6% increase in HUE when compared to state-of-the-art designs.

Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload

Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload

Research and Implementation of High-Efficiency and Low-Complexity LDPC Coding Algorithm

In this work, we proposed a high-efficiency and low-complexity encoding algorithm and its corresponding implementation structure during the design and implementation process of an LDPC encoder and decoder. This proposal was derived from extensive research on and analysis of standard encoding algorithms and recursive iterative encoding algorithms, specifically targeting the problem of high computational complexity in encoding algorithms. Subsequently, we combined binary phase-shift keying modulation mode and additive white Gaussian noise channel transmission with the min-sum decoding algorithm to realize the (1536, 1024) LDPC codec. This codec was uniformly quantized with a (6, 2) configuration, executed eight iterations, and achieved a 2/3 code rate in the IEEE802.16e standard. At the bit error rate (BER) of 10−5, the codec’s BER obtained by the proposed coding algorithm was about 0.25 dB lower than the recursive-iterative coding algorithm and was about 1.25 dB lower than the standard coding algorithm, which confirms the correctness, effectiveness, and feasibility of the proposed algorithm.

Implementation of Rate-Compatible QC-LDPC Encoder Based on FPGA

A rate-compatible LDPC encoder based on quasi-cyclic generation matrix is proposed. The encoder partitions and controls access to the ROM address, so it can be compatible with a variety of LDPC codes to generate matrix cyclic shift vectors. By adding routing options in the register cyclic shift circuit, it is compatible with matrix blocks of different sizes. Due to the adjustment of the initial shift count and the truncation of the check bit output, the virtual filling and shortening of the LDPC code is realized, which further expands the code length and code rate of the encoder. An LDPC encoder compatible with 4 code rates is implemented on a Xilinx Virtex5 xc5vfx130t FPGA, Compared with the existing design, this encoder requires only slightly more hardware resources than a single encoder to achieve the same data throughput. Compared with implementing all four different encoders, more than 40% of the hardware resources can be saved.

Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

Performance analysis of short length low density parity check codes

Outstanding bit error rate LDPC design in waterfall region and error floor region is one of the challenging tasks for the past decade. This chapter, focuses on the design of LDPC encoder with the low error floor and waterfall region of BER with minimum trapping set. Scheduled Progressive Edge-Growth (SPEG) LDPC encoder is used, and the simulation result of density evolution and exit chart are giving the better convergence of LDPC encoder. BER performance in error floor can controlled by minimum trapping set and waterfall region controlled by scheduled PEG LDPC encoder (1000, 500) with code length (n) is less than 600. The girth of the SPEG encoder is 8. SPEG with minimum trapping set will perform well for short length code also and it converges faster than the other PEG encoder.

Investigation of the Integrity of Signals in a Communication Channel Based on an LDPC Encoder

Investigation of the Integrity of Signals in a Communication Channel Based on an LDPC Encoder

EFFICIENT IMPLEMENTATION OF FPGA-BASED FORWARD ERROR CORRECTING COMBINATION AND BIT TO CELL WORD DE-MULTIPLEXER FOR A SECOND GENERATION DIGITAL TERRESTRIAL TELEVISION BROADCASTING SYSTEM

This article focus on the implementation of FEC part. The motivation of the design is that FEC is an effective tool to mitigate problems associated with OFDM which stem from multipath fading channel, high speed data rate. One of the key features of BCH codes is that during code design, there is a precise control over the number of symbol errors that are correctable by the code. BCH coder proccesses parralelly with high-speed operation. 8-bit parallel data input and output helps to maximize the throughput. DVB-T2 used LDPC coder, as inner codes with word length up to 64,800 bits, enabling significant proximity to Shannon limit. This encoder supports all code rates and both normal and short frames. Output of LDPC encoder is interleaved with bit interleaver. This project was fully optimized for speed and memory area, fully synchronized by using a single clock. The design was coded in VHDL, synthesized by using Xilinx ISE Design Suite 14.7. The design has been tested on development Kit NetFPGA-1G-CML of Digilent Corporation and the bit map was downloaded into Xilinx Kintex-7 XC7K325T-1FFG676, which is integrated on experimental transmitter system DVB-T2. This research product belong to program “Research of experimental testing of second generation digital terrestrial television broadcasting system DVB-T2” of Vietnamese Communications Television Development JSC.

Efficient QC-LDPC Encoder for 5G New Radio

This paper presents a novel efficient encoding method and a high-throughput low-complexity encoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes for the 5th-generation (5G) New Radio (NR) standard. By storing the quantized value of the permutation information for each submatrix instead of the whole parity check matrix, the required memory storage size is considerably reduced. In addition, sharing techniques are employed to reduce the hardware complexity. The encoding complexity of the proposed method was analyzed, and indicated a substantial reduction in the required area as well as memory storage when compared with existing state-of-the-art encoding approaches. The proposed method requires only 61% gate area, and 11% ROM storage when compared with a similar LDPC encoder using the Richardson–Urbanke method. Synthesis results on TSMC 65-nm complementary metal-oxide semiconductor (CMOS) technology with different submatrix sizes were carried out, which confirmed that the design methodology is flexible and can be adapted for multiple submatrix sizes. For all the considered submatrix sizes, the throughput ranged from 22.1–202.4 Gbps, which sufficiently meets the throughput requirement for the 5G NR standard.

Hybrid Concatenated LDPC Codes with LTE Modulation Schemes

In a communication system, the LDPC code is considered as a good performance error correcting code which reaches near Shannon limit. In this paper a hybrid LDPC code is proposed, the hybrid term here refers to the serial concatenation of parallel LDPC codes group and a single serial LDPC code. The outer two parallel LDPC codes encoder represents outer encoder where the single LDPC encoder represents the inner encoder. This study also emphases on the performance of a hybrid coding system in consideration with three modulation schemes. The modulation schemes include quadrature phase shift keying (QPSK) and two types of quadrature amplitude modulation; 16-QAM and 64-QAM. These modulation schemes are selected due to their importance in modern communication applications, such as long term evolution (LTE); such schemes are the standard modulation schemes used with LTE system. This study investigates different LDPC code rates such as 1/2 and 1/3 and simulates the AWGN communication channel using MATLAB. The simulation results show improvement in bit error rate (BER) when using 1/3 LDPC code rate in the designed system rather than 1/2, but it also increases the system complexity. In the end, all simulation results, the comparison between different cases of LDPC code rates and system performance are summarized.

Adaptive low density parity check encoder for a complete free space optics/continuous variable-quantum key distribution system using commercially available off-the-shelf devices for variable throughput network considering dynamical atmospheric turbulence levels

In this paper, an adaptive LDPC encoder for complete FSO/CV-QKD system using a COTS device for emulated dynamical atmospheric turbulence levels is presented. The experimental and emulation results show the maximum and minimal final secret key rates of 105 Kbps and 10 Kbps, respectively, for minimal and maximal throughput in a commercial network, 30 Mbps and 90 Mbps, respectively. Our proposal presents an adequate performance for weak and moderate atmospheric turbulence levels and a suitable option for improve the using of QKD systems.

위성 방송 시스템에서 최적의 고전송 효율 기법 연구

차세대 위성 방송 시스템에서는 빠른 전송 효율과 신뢰도 있는 통신에 대한 요구가 지속적으로 증가하고 있다. 전송 효율을 높이고 성능을 향상시키기 위해 새로운 위성 표준 인 DVB-S3 (Digital Video Broadcasting - Satellite - Third Generation) 시스템에서는 Nyquist 전송률 보다 빠르게 전송하는 FTN (Faster Than Nyquist) 방식이 대두되고 있다. 이러한 요구에 맞춰 본 논문에서는 전송 효율 향상을 위한 세 가지 방식에 대한 성능을 비교 분석하였다. 기존의 LDPC 부호기에서 고 부호화율 방식과 LDPC 복호화 과정에서 생선된 check node를 이용하여 bit node를 puncturing시켜 부호화율 증가 시키는 punctured LDPC 방식, 그리고 Nyquist 속도보다 빠르게 전송하는 FTN 방식이 고려된다. 시뮬레이션을 통해, 세 가지 방식을 동일 전송률 관점에서 성능을 비교한 결과 FTN 방식은 동일한 전송 효율을 유지하면서 성능 면에서 가장 효율적임을 확인하였다. In next generation satellite broadcasting system, requirement of high throughput efficiency has been increasing continuously. To increase throughput efficiency and improve bit error performance simultaneously, FTN method and LDPC codes are employed in new sattelite standard, DVB-S3 system. This paper considered three kinds of methods for increase throughput efficiency. Firstly, as conventional one, high coding rate parity matrix in LDPC encoder is considered. Secondly, punctured coding scheme which delete the coded symbols according to appropriate rules is considered. Lastly, FTN method which transmit fater than Nyquist rate is considered. Among of three kinds of methods, FTN method is most efficient in aspect to performance while maintain same throughput efficiency.

Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N

Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N

Multi-rate LDPC encoder for high-speed satellite data transmissions

Multi-rate LDPC encoder for high-speed satellite data transmissions

Comprehensive Algorithmic Review and Analysis of LDPC Codes

Due to the increasing popularity of LDPC codes and its demand for future applications, first time in this paper, LDPC coding techniques have been systematically summarized and analyzed. The paper gives the comprehensive review of LDPC encoder, decoder and its architecture for simulation and implementation. The paper is specially intended for giving an insight of the algorithmic overview of the LDPC encoder, decoder and its architecture for research and practical purposes. The original belief propagation algorithm (BPA) , logarithmic model of BPA , and the other simplified form of the logarithmic sum product algorithms (SPA) has been elaborated and analyzed for medium and short length codes under AWGN channel

Comprehensive Algorithmic Review and Analysis of LDPC Codes

Due to the increasing popularity of LDPC codes and its demand for future applications, first time in this paper, LDPC coding techniques have been systematically summarized and analyzed. The paper gives the comprehensive review of LDPC encoder, decoder and its architecture for simulation and implementation. The paper is specially intended for giving an insight of the algorithmic overview of the LDPC encoder, decoder and its architecture for research and practical purposes. The original belief propagation algorithm (BPA) , logarithmic model of BPA , and the other simplified form of the logarithmic sum product algorithms (SPA) has been elaborated and analyzed for medium and short length codes under AWGN channel

Analysis of Minimal LDPC Decoder System on a Chip Implementation

This paper presents a practical method of po- tential replacement of several different Quasi-Cyclic Low- Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to imple- ment the LDPC encoder and decoder in a memory-con- strained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algo- rithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the pro- posed LDPC setup simplification. Finally, the error per- formance of the modified system structure is evaluated and compared with the original system structure by means of simulation.

The Design of LDPC Encoder Based on the WIMAX Standard

To meet the higher data rate requirement of encoder, an encoder structure suitable for both two rates(1/2,2/3B) in WIMAX standard is proposed, combined with the method of Design Space Exploration. According to the quasi cyclic characteristics of sparse parity check matrix, the traditional RU algorithm is simplified and optimized to reduce the complexity of the system. Simultaneously we introduce a barrel shifter, and use the method that two rows of the base matrix be restored in one ROM to reduce resource consumption. The simulation results show that the encoder for two rates not only runs successfully, but also reduces the utilization of hardware resources. The encoder architecture has broad application prospects with high flexibility.

The Design of LDPC Encoder Based on the WIMAX Standard

The Design of LDPC Encoder Based on the WIMAX Standard