Abstract
This paper presents a practical method of po- tential replacement of several different Quasi-Cyclic Low- Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to imple- ment the LDPC encoder and decoder in a memory-con- strained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algo- rithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the pro- posed LDPC setup simplification. Finally, the error per- formance of the modified system structure is evaluated and compared with the original system structure by means of simulation.
Highlights
The shortening of Reed Solomon (RS) codes presents a known and widely used technique of code parameter adaptation for practical implementations
This paper presents a practical method of potential replacement of several different Quasi-Cyclic LowDensity Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC)
Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification
Summary
The shortening of Reed Solomon (RS) codes presents a known and widely used technique of code parameter adaptation for practical implementations. This paper elaborates on this analysis by providing insight not just regarding the code structure, and analyzing the effect of variable node value fixation on practical Belief Propagation (BP) decoding algorithms. This text focuses on the even more practical approach – evaluation of potential LDPC decoder with respect to the limitations of a resource limited System on a Chip (SoC) implementation. The final section contains a brief summary and concludes the paper
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