Abstract
Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N
Highlights
In recent years, Low -density parity –check codes [1], which were first proposed by R
LDPC codes are linear block codes that can be denoted as (n, k) or (n, wc, wr), where n is the length of the codeword, k is the length of the message bits, wc is the column weight, and wr is the row weight
The proposed encoder architectures have been implemented in hardware for IEEE 802.11 QCLDPC defined by the parity- check matrix given by the standard for codeword length n = 648 bits, rate1/2 and block size z = 27.Table IV lists the corresponding occupied area in the Xilinx Virtex-5 FPGA device xc5vlx110t-1ff1136
Summary
Low -density parity –check codes [1], which were first proposed by R. Low complexity of the encoder can be achieved by using structured LDPC codes. Many encoding algorithms were used in the past, it is suggested that the encoding complexity can be significantly reduced by using an approximate upper triangular parity check matrix to construct LDPC codes. We have adopted structured LDPC codes known as the Quasi-cyclic Low-density parity check codes. Quasi-Cyclic has been proposed to reduce the complexity of LDPC while obtaining the similar performances. In QC-LDPC codes, the parity check matrix is a sparse. Most commonly lower-triangular matrix algorithm is used to simplify the encoding methods as suggested in Richardson and Urbanke method [4]. The encoder based on Richardson and Urbanke algorithm [3] which provides effective linear running time for some codes with a sparse paritycheck matrix. The encoding throughputs are determined by using encoding clock frequency and number of encoding iterations
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