LDMOS Devices Research Articles

Low Specific On-resistance SOI LDMOS Device with P+P-top Layer in the Drift Region

In this paper, a novel low specific onresistance SOI LDMOS Device with P<SUP>+</SUP>P-top layer in the drift region is proposed and investigated using a two dimensional device simulator, MEDICI. The structure is characterized by a heavily-doped P<SUP>+</SUP> region which is connected to the P-top layer in the drift region. The P<SUP>+</SUP> region can modulates the surface electric field profile, increases the drift doping concentration and reduces the sensitivity of the breakdown voltage on the geometry parameters. Compared to the conventional D-RESURF device, a 25.8% decrease in specific on-resistance and a 48.2% increase in figure of merit can be obtained in the novel device. Furthermore, the novel P<SUP>+</SUP>P-top device also present cost efficiency due to the fact that the P<SUP>+</SUP> region can be fabricated together with the P-type body contact region without any additional mask.

A modified LDMOS device with improved ESD protection performance

A modified lateral‐diffusion metal–oxide–semiconductor (MLDMOS) device with improved electrostatic discharge (ESD) protection performance is proposed for high‐voltage ESD protection. In comparison with the traditional LDMOS and the LDMOS with an embedded silicon‐controlled rectifier (LDMOS‐SCR), the proposed device has better ESD robustness and higher holding voltage. By optimizing key parameters, such as the spacing between the drain and the poly gate, the effective channel length, and the number of fingers, the MLDMOS can achieve a maximum failure current over 80 mA/µm, which is larger than that of LDMOS‐SCR. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.

Combined MOS–IGBT–SCR Structure for a Compact High-Robustness ESD Power Clamp in Smart Power SOI Technology

Smart power technologies are required to withstand high-electrostatic-discharge (ESD) robustness under both powered and unpowered conditions, particularly for automotive and aeronautic applications among many others. They are concurrently confronted to the challenges of high-temperature operation in order to reduce heat-sink-related costs. In this context, very compact high-robustness ESD protections with low sensitivity to temperature are required. To fulfill this need, we studied a new ESD protection structure that combines in the same component MOS, IGBT, and thyristor effects. This is achieved by inserting in the same LDMOS device P+ diffusions in the drain. We studied the impact of N+/P+ ratios on RON and holding current at high temperatures. Structure optimization has been realized with 3-D TCAD simulation and experimentally validated. The proposed structures provide high ESD robustness with small footprint and reduced temperature sensitivity compared with classical solutions. Original design solutions to improve their immunity to latchup are also presented.

Analytical compact modeling and statistical variability study of LDMOS

In this paper, we present an analytical IV model for high-voltage LDMOS. The model is surface potential based, and explicit calculation of the internal drain voltage is achieved by unified regional formulation of the drift resistance. High-voltage effects such as quasi-saturation and impact ionization are well captured. The compact model is verified with TCAD simulations and measurement data in all operating ranges. In addition, this model is utilized to study the statistical variability in LDMOS devices. Under the assumption of uncorrelated normal distribution of device parameters, variations in physical device parameters can be directly related to the variations in performance target variables with the aid of the compact model, which can be useful in device optimization.

An RF LDMOS with excellent efficiency and ruggedness based on a modified CMOS process

Two types of RF LDMOS devices, specified for application in the driver stage and output stage of a power amplifier, are designed based on a modified CMOS process. By optimizing the layout and process, the output capacitance per unit of gate width is as low as 225 fF/mm. The driver stage and output stage devices achieve an output power of 44 W with a PAE of 82% and 230 W with a PAE of 72.3%, respectively (P3dB compression) at 1 GHz. Both devices are capable of withstanding extremely severe ruggedness tests without any performance degradation. These tests are 3–5 dB overdrive, 10:1 voltage standing wave ratio mismatch load through all phase angles, and 40% drain overvoltage elevation at a working point of P3dB.

An analytical model for the drain—source breakdown voltage of RF LDMOS power transistors with a Faraday shield

An analytical model for the drain—source breakdown voltage of an RF LDMOS power transistor with a Faraday shield is derived on the basis of the solution of the 2D Poisson equation in a p-type epitaxial layer, as well as an n-type drift region by means of parabolic approximation of electrostatic potential. The model captures the influence of the p-type epitaxial layer doping concentration on the breakdown voltage, compared with the previously reported model, as well as the effect of the other device parameters. The analytical model is validated by comparing with a numerical device simulation and the measured characteristics of LDMOS transistors. Based on the model, optimization of LDMOS device parameters to achieve proper trade-off between the breakdown voltage and other characteristic parameters such as on-resistance and feedback capacitance is analyzed.

A compact model for the ion implanted channel LDMOS transistor

This paper presents a compact model for the lateral double-diffused MOS transistor in which ion implantation is employed in the channel region. We show that the conventional LDMOS device models which do not include specifics of the implanted channel region cannot accurately predict behavior of such structure. We then propose a new physics based model which employs surface potential in the device. The model gives a robust formulation for both the channel and the drift regions and can accurately describe the performance of the ion implanted channel LDMOS structure.

Device simulation of a novel strained silicon channel RF LDMOS

. ► Novel strained silicon LDMOS structure has been proposed. ► Its output characteristics have been compared with that of a conventional LDMOS device. ► Strain layer leads to a great improvement in the device performance ( Table 1 ). ► Capacitance–voltage characteristics of the proposed device is examined. In this paper we propose a novel RF LDMOS structure which employs a thin strained silicon layer at the top of both the channel and the N-Drift region. The strain is induced by a relaxed Si 0.8 Ge 0.2 layer which sits on top of a compositionally graded SiGe buffer. We have used a 2D device simulator to investigate improvements in the output characteristics of the device including saturation and linear transconductance, current drivability, cut off frequency and the on resistance. Furthermore we have examined the capacitance voltage behavior of the proposed strained silicon LDMOS device and have compared it with that of the conventional LDMOS device. It is observed that the gate capacitance increases in strong inversion with strain, but remains relatively unaffected in depletion and accumulation modes of the device operation.

Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

This paper presents device optimization and physical analysis based on gate-grounded NMOS (GGNMOS) and n-channel lateral DMOS (nLDMOS) devices manufactured in a 0.35μm 5V/30V high-voltage BCD process. The multiple body pick-up technique has been investigated in detail for the GGNMOS, and the robustness and effectiveness of the LDMOS device is optimized by tuning the drain contact to gate space (DCGS) and increasing the body resistance. Finally, the trigger voltage walk-in effect is observed for the nLDMOS device and is studied by comprehensive simulation and TLP tests.

Characterization and modelling of single event transients in LDMOS-SOI FETs

In this paper, we develop a model to simulate the single event transient (SET) phenomena in LDMOS-SOI devices. 3D simulations and compact model are coupled in order to reproduce the current pulse in LDMOS-SOI device generated by an ion strike through the different device locations, at various biases and temperatures. Obtained results allow for identifying the effects to be taken into account for accurate transient description. Furthermore, comparison with SET observed in Partially Depleted SOI MOSFET reveals that LDMOS device exhibits lower drain current upset whereas larger recovery time, which results in higher collected charge.

MOS-IGBT power devices for high-temperature operation in smart power SOI technology

We propose a new MOS-IGBT device with improved characteristics for high-temperature operation. It is achieved by inserting in the same LDMOS device P+ diffusions in the drain with various N+/P+ ratios. 3D TCAD simulations are used to optimize the original structure in particular, to validate drain and source engineering solutions aimed at providing a latch-up free operation.

HHNEC 0.18um BCD Technology for High Density Power Integration

A new 0.18um Bipolar CMOS DMOS (BCD) integrated platform is presented. This technology provides both N type and P type power LDMOS with capability of voltage up to 40V applications; these power LDMOS devices have competitive specific on-resistance; the parasitical miller capacitance and SOA of power LDMOS devices are optimized by careful device and layout design; it also provides HVCMOS with voltage up to 40V analog application; the bipolar devices in this technology are also optimized for power switching as standard bipolar process offers. The 1.8V/5.0V CMOS devices are performance compatible with industry main stream 1.8V/5.0V CMOS technology. This platform is modularized with various options; it can be separated into 1.8V/5.0V mixed 40V HVCMOS process, 5.0V Vgs 40V Vds 0.18um backend BCD process and 1.8V/5.0V Vgs 40V Vds 0.18um BCD process, which customers can easily choose for their product needs without any process tuning.

Radiation Studies of Power LDMOS Devices for High Energy Physics Applications

We present radiation hardness studies performed on LDMOS devices included in a 0.25 μm SiGe BiCMOS technology from IHP Microelectronics. Results show degradation of devices performances only beyond 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> n <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eq</sub> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Combining 2D and 3D Device Simulations for Optimizing LDMOS Design

Lateral DMOS power devices can achieve high breakdown voltage by optimizing the two dimensional (2-D) device parameters in accordance with the RESURF principle. However, in practice, it is also necessary to optimize the three dimensional (3-D) device parameters in order to support a given breakdown voltage. In this paper, We report the effect of 3-D parameters such as the curvatures of the drain and source regions, doping density of LDMOS device with SOI (Silicon-On-Insulator) substrates based on numerical simulations and analytical solutions using cylindrical coordinates with device simulator "MEDICI" and Synopsys 3D simulator Sentaurus 2009.06-SP2 version. We stress the necessary 3D simulation for power device with racetrack, interdigitated layouts etc.

Partial SOI superjunction power LDMOS for power IC applications

An enabling superjunction device technology, which is fully integrated on the partial silicon on insulator (PSOI) platform using the bulk silicon substrate, is proposed and fabricated. The proposed technology has the potential to eliminate the substrate assisted depletion. It enables the implementation of lateral superjunction power MOSFET (SJ LDMOS) on bulk silicon substrate without sacrificing its thermal performance. In this paper, the approach was demonstrated successfully on both p-i-n diode and planar gate SJ LDMOS devices. The proposed technology has enabled the fabrication of SJ power integrated circuits (PIC) on the bulk silicon substrate for future automotive power electronics applications.

Peak Class F and Inverse Class F Drain Efficiencies Using Si LDMOS in a Limited Bandwidth Design

This paper compares two popular high power, high efficiency modes of operation, class F and inverse class F, and assesses the peak obtainable drain efficiencies when using Si LDMOS devices in a limited bandwidth design. Optimum class F and inverse class F conditions are presented using active harmonic load-pull measurements, and it was found that a higher drain efficiency was achieved in the class F configuration. This result is due to the limitations imposed by the soft voltage breakdown occurring due to the extended voltage swings inherent to inverse class F, as a consequence generating unwanted current content during the off cycle. This significantly reduces the peak measured efficiency using Si LDMOS devices when implementing an inverse class F design with a drain bias of 28 V. By reducing the drain bias to 18 V, to accommodate the voltage extension of inverse class F, it became possible to achieve peak measured efficiencies much closer to what theory predicted.

A Novel RF LDMOS Fabricated With Standard Foundry Technology

In this letter, a novel LDMOS structure is proposed and experimentally demonstrated with standard foundry CMOS technology. The device features both an inserted oxide layer in the drift region as the ldquoelectric field line absorberrdquo and a high-doped region introduced for action of the RESURF-like structure. The RESURF-Dielectric-region-Inserted LDMOS device with breakdown voltage of about 15 V and peak cutoff frequency of 18 GHz is obtained. The proposed device also exhibits good reliability behavior under high-voltage stressing. The new device is very promising for integrated power amplifier circuit design with the standard CMOS process.

Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I DS and different extremes temperatures Δ T values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO 2 interface.

2-D simulation and analysis of temperature effects on electrical parameters degradation of power RF LDMOS device

This paper presents a synthesis of temperature effects on power RF Laterally Diffused (LD) MOS performances, which can modify and degrade transistor physical and electrical behaviour. In this work, the temperature influence on device electrical characteristics is discussed with regard to physical limits for device operation. A developed 2-D structure was implemented and simulated using the physical simulator Silvaco-Atlas to explain the observed data and offer insight into the physical origin of LDMOS temperature behaviour. The temperature dependence of most important electrical parameters such as channel current Ids, threshold voltage Vth and inter-electrodes capacitances (Cds, Cgs) is investigated. The temperature effects on mobility, electron concentration, electric field, current flow lines and Fermi level are taken into account. Finally, initial failure analysis is discussed.

Scalable general high voltage MOSFET model including quasi-saturation and self-heating effects

In this work, we present for the first time, a highly scalable general high voltage MOSFET model, which can be used for any high voltage MOSFET with extended drift region. This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, and a new general model for drift resistance. The model is validated on the measured characteristics of two widely used high voltage devices in the industry i.e. LDMOS and VDMOS devices, and implemented on commercial circuit simulators like SABER (Synopsys), ELDO (Mentor Graphics), Spectre (Cadence) and UltraSim (Cadence). The accuracy of the model is better than 10% for DC I–V and g–V characteristics and shows good behavior for all capacitances which are unique for these devices showing peaks and shift of peaks with bias variation. The model also exhibits excellent scalability with transistor width, drift length, number of fingers and temperature.