LC Voltage-controlled Oscillator Research Articles

A 0.73 mW low power 9.6 GHz LC voltage-controlled oscillator achieves constant KVCO and −189.2 FOM

This article introduces a novel approach of LC voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications and proposes a 9.6 GHz VCO based on gm-boosted structure. By utilizing a transformer and gain variation calibration technique, the proposed VCO reduces the losses caused by MOSFET’s operation in triode region, thereby improving phase noise. And KVCO remains relatively constant, fluctuating up and down by approximately 5 MHz around 100 MHz/V, which is suitable to be used in phase-locked-loops (PLL). The oscillator is fabricated in 22 nm CMOS process occupying 0.25 mm × 0.55 mm area and consuming 0.73 mW from 0.5 V supply voltage. The measured phase noise achieves −114.3 dBc/Hz at 1 MHz offset with a carrier frequency of 4.75 GHz, and the figure of merit (FoM) is −189.2 dBc/Hz. The results clearly demonstrate that the proposed design could work under low power consumption and achieve constant KVCO, making it well suitable for high-frequency PLL applications.

High data rate and energy efficient configurable IR-UWB transmitter with an integrated balun

This paper presents a novel, digitally configurable, switching oscillator-based impulse radio ultra-wideband (IR-UWB) transmitter that is robust to process variations. The pulse width and pulse position properties of the output waveform are configurable to ensure operation for the desired bandwidth and output pulse energy values. The architecture is based on a cross-coupled LC voltage-controlled oscillator (LC VCO) implemented with a custom-designed on-chip balun at a center frequency of 2.4 GHz. With the usage of this on-chip balun, the need for an extra buffer stage is eliminated, and the highest possible efficiency is achieved with the proper turns ratio selected. The generated digital control pulse signals are also used to ensure fast start-up and UWB operation while maintaining low power consumption with an implemented on/off tail switching scheme. The presented IR-UWB transmitter that occupies a total area of 0.35 mm2 is fabricated in the United Microelectronics Corporation (UMC) 180-nm mixed-mode/radio frequency (RF) CMOS process. The measured output voltage swing of the fabricated transmitter is 0.812 V on a 50-Ω load for the 200 Mb/s data rate, and the bandwidth is measured as 902 MHz. The achieved frequency tuning range is 1 GHz and the fabricated transmitter can drive 50 Ω, 75 Ω and 100 Ω loads with measured efficiency values 4.16%, 5.76%, and 4.05%, respectively. Compared to other works in the literature, this design achieves a higher output pulse energy at a higher data rate while maintaining low power consumption and, thus, high efficiency.

An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz

A low-power single-core 24.5-to-29.1 GHz CMOS LC voltage-controlled oscillator (VCO) is presented. The proposed VCO uses an innovative differential cross-coupled architecture in which an additional pair is connected to the main pair to increase the effective transconductance, resulting in lower power consumption and reduced phase noise (PN). The proposed VCO is fabricated in a 1P9M standard CMOS process and sustains oscillation at 29.14 GHz with power consumption as low as 455 μW (650 μA from a 0.7 V supply), which is ~20% lower than a conventional CMOS LC VCO without Gm-enhanced differential pairs built through the same process (700 μA from 0.8 V supply). When consuming 880 μW (1.1 mA from 0.8 V), the proposed VCO exhibits a tuning range of 4.6 GHz (from 24.5 GHz to 29.1 GHz). Moreover, it exhibits a measured phase noise (PN) better than −106.5 dBc/Hz @ 1 MHz and −132.0 dBc/Hz @ 10 MHz, with figure-of-merit (FoM) results of 195.2 dBc/Hz and 200.3 dBc/Hz, respectively.

A Low-Power, 65 nm 24.6-to-30.1 GHz Trusted LC Voltage-Controlled Oscillator Achieving 191.7 dBc/Hz FoM at 1 MHz

This work presents a novel trusted LC voltage-controlled oscillator (VCO) with an embedded compact analog Physically Unclonable Function (PUF) used for authentication. The trusted VCO is implemented in a 1P9M 65 nm standard CMOS process and consumes 1.75 mW. It exhibits a measured phase noise (PN) of −104.8 dBc/Hz @ 1 MHz and −132.2 dBc/Hz @ 10 MHz offset, resulting in Figures of Merit (FoMs) of 191.7 dBc/Hz and 199.1 dBc/Hz, respectively. With the measured frequency tuning range (TR) of ~5.5 GHz, the FoM with tuning (FoMT) reaches 197.6 dBc/Hz and 205.0 dBc/Hz at 1 MHz and 10 MHz offset, respectively. The analog PUF consists of CMOS cross-coupled pairs in the main VCO to change analog characteristics. Benefiting from the impedance change and parasitic capacitance of the cross-coupled pairs, the AC and DC responses of the VCO are utilized for multiple responses for each input. The PUF consumes 0.83 pJ/bit when operating at 1.5 Gbps. The proposed PUF exhibits a measured Inter-Hamming Distance (HD) of 0.5058b and 0.4978b, with Intra-HD reaching 0.0055b and 0.0053b for the current consumption and fosc, respectively. The autocorrelation function (ACF) of 0.0111 and 0.0110 is obtained for the current consumption and fosc, respectively, at a 95% confidence level.

A high‐linearity LC‐VCO with combined MOS varactors and bulk‐biased PMOS varactors for gain variation compensation

AbstractA high‐linearity LC‐voltage‐controlled oscillator (LC‐VCO) with combined metal‐oxide semiconductor varactors and bulk‐biased P‐channel metal‐oxide semiconductor varactors in parallel is proposed to reduce the VCO‐gain (KVCO) variation and extend the linear range of the control voltage. Fabricated in a 180‐nm complementary metal‐oxide semiconductor process, the proposed topology achieves a low gain variation of less than 6.3% and a tuning range of ~28% operating from 2.31 to 3.06 GHz, corresponding to a linear control voltage range from 0.6 to 1.4 V. The phase noise is measured to be −115.3 dBc/Hz at 1 MHz offset at 3.06 GHz and the figure of merit (FoM) is −181.2 dBc/Hz. The oscillator occupies an area of 0.93 × 0.54 mm and consumes 1.8 mW from mixed 1.2/1.8 V supply voltage.

K‐band CMOS voltage‐controlled oscillator using switched self‐biasing technique

AbstractA complementary metal oxide semiconductor (CMOS) voltage‐controlled oscillator (VCO) using a tail current source modulated with the output frequency is presented to achieve low phase noise with low power consumption at the K‐band. Differentially modulated current sources, which reduce flicker noise by the feedback of the VCO outputs, contribute to an overall reduction in the phase noise of the VCO using the electromagnetic‐based fully symmetrical design. The proposed LC VCO with a 3‐bit switched capacitor bank for a wide tuning range was fabricated on the size of 0.4 × 0.57 mm2 using a 65‐nm CMOS process. The measurement results of the proposed VCO showed a frequency tuning range from 22.57 to 25.3 GHz, and a phase noise of −108.48 dBc/Hz at a 1‐MHz offset frequency with a power consumption of 8.27 mW at a supply voltage of 1.2 V. The calculated figure of merit (FoM) and FoM with the tuning range were −186.48 and −187.67 dBc/Hz, respectively.

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

A Frequency-Tunable Fractional-N PLL for High-Energy Physics Experiments

A frequency tunable phase-locked loop (PLL) applied in high energy particle detector has been developed. In order to achieve high detection efficiency, high requirements are promoted for on-chip clock in CMOS pixel sensors, which requires high precision and low power consumption for the PLL. The proposed PLL employs a fractional-N frequency division structure. An LC voltage-controlled oscillator (LC-VCO) is used to generate the local clock. A third-order MASH sigma-delta (Σ - Δ) modulator is used to alleviate the quantization noise introduced by the fractional-N frequency divider. In order to further reduce the phase noise, pre-set and post-set binary frequency dividers are employed. In the prototype chip a low dropout regulator (LDO) is integrated to suppress the power supply noise. The PLL was designed and fabricated in a 180 nm CMOS process. It costs an area of 1.29 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a power of 8.1 mW at a 1.8 V power supply. The measured output frequency range is 400 - 530 MHz with the reference frequency of 25 - 35 MHz. The RMS jitter, integrated from 100 kHz to 100 MHz, is 4.8 ps at 526 MHz. The in-band spur is less than -61 dBc, and the phase noise at 1 MHz frequency offset is less than -113 dBc/Hz.

A Low Gain Variation LC-VCO With Mutual Inductive Tuning for K VCO Linearity Compensation

A high-linearity LC-voltage-controlled oscillator (LC-VCO) with a mutual coupled inductive tuning technique is proposed to reduce VCO-gain ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K_{\mathrm {vco}}$ </tex-math></inline-formula> ) variation induced by varactors in finite linear region. The oscillator is fabricated in a standard 180-nm CMOS process occupying 0.88 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times0.9$ </tex-math></inline-formula> mm and consuming 3.6 mW from mixed 0.9/1.8 V supply voltage. With the variable effective inductance of the resonant tank, the proposed topology achieves a low gain variation of less than 6.1%, possessing a linear-tuning control voltage range from 0.5 to 1.8 V and operating from 3.40 to 4.04 GHz. The phase noise is measured to be −108.59 dBc/Hz at 1 MHz offset with a carrier frequency of 4.04 GHz, and the figure of merit (FoM) is −173.8 dBc/Hz.

An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm

The developing optimization algorithms provide promising solutions for speeding up analog integrated circuit sizing. However, the optimization of complicated circuits whose solution regions are narrow remains to be a challenge. With a limited number of sampling points due to the restriction of computational resources, it is difficult for traditional algorithms to achieve satisfactory results for such circuits. To solve this problem, this article proposes a rule-guided genetic algorithm (RG-GA) for analog circuit optimization. Different from the random mutation approach in the traditional genetic algorithm (GA), the RG-GA introduces a design rule-guided mutation (RGM) mechanism which helps to find the solution region in a more straightforward fashion. Instead of handing over circuit optimization tasks to pure mathematical algorithms, the proposed method takes advantages of valuable design knowledge to improve searching efficiency. This novel algorithm is implemented and deployed to design a two-stage rail-to-rail operational amplifier (OPA), an LC voltage controlled oscillator (LC-VCO) and a four-stage OPA. Experimental results show that compared to the traditional GA method, the RG-GA achieves about 1.5 and 3.3 times speed enhancement for the two-stage rail-to-rail OPA and the LC-VCO, respectively. For the four-stage OPA, the RG-GA method can find an acceptable point within the given number of iterations while the traditional GA could not.

Wide-tunable LC-VCO design with a novel active inductor

This paper presents the design of a wide-tunable, low-voltage, small-area LC voltage-controlled oscillator (LC-VCO). Instead of a spiral inductor, a novel active inductor is used in the conventional bottom-biased NMOS cross-coupled LC-VCO architecture. The oscillator, designed in TSMC 65 nm CMOS process and post-layout simulated in Cadence Design Suite, operates at a frequency range of 2.4 to 3.8 GHz and draws 8.5 mA from a 1.2 V supply. At a 1 MHz offset, the circuit has a phase noise of −80.22 dBc/Hz. The designed circuit has a differential output swing of 56.1 mV, and the percentage of total harmonic distortion (%THD) is determined as 3.47% in the nominal case. The designed LC-VCO consumes only 0.013 mm2 silicon area. Additionally, a buffer circuit is presented that can be utilized to make the oscillation rail-to-rail.

Phase Noise Reduction in LC VCO’s Using an Array of Cross-Coupled Nanoscale MOSFETs and Intelligent Post-Fabrication Selection

Low-frequency mymargin noise, thermal noise, and dc characteristics of nanoscale MOS transistors with dimensions close to the process minimum are highly variable. This article demonstrates a phase noise (PN) reduction technique for LC voltage-controlled oscillators (VCOs) that use an intelligent post-fabrication selection of a subset of an array of near minimum-size cross-coupled transistor pairs with reduced low-frequency noise and thermal noise. Using the technique, the PN of a VCO is lowered from the maximum by 3.5 dB at 600-kHz, 1-MHz, and 3-MHz offsets from a 3.8-GHz carrier. The lowest PN of −122, −129, and −139.5 dBc/Hz at 600-kHz, 1-MHz, and 3-MHz offsets, respectively, from a 3.8-GHz carrier has been measured using the PLL method of the Keysight E5052B Signal Source Analyzer. The VCO prototype was fabricated in a 65-nm CMOS process and dissipates 7 mW of dc power. The maximum figure of merit (FoM), including PN, carrier frequency, and power consumption, is 193 dBc/Hz, and the FoM, including the VCO core area, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {FoM}}_{A}$ </tex-math></inline-formula> , is 209 dBc/Hz.

Design and implementation of a second order PLL based frequency synthesizer for implantable medical devices

In this paper, a low power 450 MHz frequency synthesizer for implantable medical device (IMD) is presented. A current-reuse LC voltage-controlled oscillator is used to lower the power consumption of the frequency synthesizer. A prototype is fabricated in a standard 130 nm CMOS technology with an active area of 0.099 mm2. The design performance parameters are measured for different packaged prototypes and the performance is evaluated. The power consumption of the frequency synthesizer is 0.74 mW at an oscillating frequency of 450 MHz. The measurement results show a figure-of-merit (FOMpower) of 1.65 for a VDD of 1.2 V.

A Transformational Framework for Analysis of Phase Noise in LC Oscillators

Phase noise has become the single most critical factor to be addressed in the design of modern communication systems. Facing the challenging requirements of 5G cellular communication, our paper describes a new theoretical framework to calculate the phase noise of LC oscillators, relying on easy to implement closed form solutions for phase noise calculations. Using closed form phase noise solutions enables oscillator designers to easily implement multiple phase noise calculation options for a number of oscillator circuits, which would be very difficult to implement with the existing mathematically complex phase noise theories. The analytic methods of our theory rely on modeling all real oscillators as having non-ideal or latent behaviors in addition to their primary nature for generating a carrier wave operating at a single frequency with a single amplitude. It is a cascade of these non-ideal transformation processes that produce non-ideal oscillator outputs containing the phase noise sidebands. Enhanced qualitative and quantitative insights into oscillator phase noise performances are achieved by using this approach. We validate our methods by comparing their results with phase noise simulations carried out for a sample CMOS LC voltage-controlled oscillator in 90 nm RFCMOS process using SpectreRF simulator. The results for the oscillator's output 1/f2 thermal phase noise, 1/f noise upconversion into 1/f3 phase noise and the 1/f3 corner frequency of phase noise spectrum using our theory yields −136 dBc/Hz at 10 MHz offset, −21.3 dBc/Hz at 1 kHz offset and 2.6 MHz respectively. The corresponding values obtained with SpectreRF simulation are −135.9 dBc/Hz, −23.4 dBc/Hz and 2.1 MHz. The carrier frequency is 5.4 GHz with output power of 9.78 dBm.

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.

Effect of Tail Capacitor on Phase Noise in LC Cross-connected Oscillators: An Analytical Investigation

This paper investigates the effect of tail capacitance on phase noise of an LC-VCO (LC voltage-controlled-oscillator). First, the analytical relations of the phase noise for different values of tail capacitor (CT) are derived and then for verifying them, simulation and calculated results are compared. For simplicity, three scenarios such as small, medium and large values of CT are considered. In a case study an LC-VCO is designed in a standard 0.18µm CMOS technology, and simulation and numerical results have been presented for different values of CT. In this case study, numerical analysis shows that for CT =200fF (medium CT) and CT =10pF (large CT), the phase noise at 1MHz offset from the 5.2GHz is -96dBc/Hz and -118dBc/Hz, respectively. According to the results, the ISF (Impulse sensitivity function) is improved by increasing the amount of CT. Numerical values also demonstrate that excessive increase of CT has no effect on the phase noise. While choosing bigger CT can effectively reduce the noise contribution of the tail by bypassing the noise of tail transistor, but low impedance path generated by CT may degrade the phase noise by reducing tank quality factor.

Design of optimal high-frequency CMOS VCOs for automotive application

In this paper, a design methodology of Voltage-Controlled Oscillator (VCO) for long-range automotive RAdio Detection And Ranging (RADAR) is proposed and simulation analysis is carried out over Virtuoso SpectreRF software on Cadence tool. The frequency ranges of the mm-wave CMOS current-starved ring and LC VCOs for 45-nm CMOS technology are 24 and 76 GHz, respectively. The ring VCO at 25 GHz oscillation frequency demonstrates 2.06% tuning range, phase noise −71.61 dBc/Hz at 1-MHz offset, 3.43 mW power dissipation and layout area of $$20\times 20 \,\upmu {\mathrm{m}}^2$$ whereas cross-coupled LC VCO achieves an oscillation frequency of 76.25 GHz for frequency tuning range of 0.65%, a phase noise of −92.44 dBc/Hz at 1-MHz offset, 8.59 mW power dissipation and $$320\times 320 \,\upmu {\mathrm{m}}^2$$ layout area. The proposed design of efficient VCOs shows an excellent performance for long-range automotive RADAR.

A 17.6-to-24.3 GHz −193.3 dB figure-of-merit LC voltage-controlled oscillator using layout floorplan optimization technique for Q-factor enhancement

This paper presents a 20 GHz low-phase-noise low-power LC voltage-controlled oscillator (VCO). It adopts a fully differential tuning varactor, a coarse and a fine capacitor array to cover wide tuning range with a small tuning gain to reduce the amplitude-to-phase noise conversion. A layout floorplan is proposed to reduce the impact of the parasitic resistance of the interconnect and thus improve the Q of the LC tank in the VCO. Hence, the phase noise can be reduced without increasing power consumption. Post-layout simulation results show that the VCO with the proposed layout floorplan can get the phase noise reduction from 1.6 to 3.3 dB compared to the VCO with other layout floorplans in the case of the same power consumption. Implemented in a 65 nm CMOS process, the prototype achieves 17.6–24.3 GHz frequency range, −124 dBc/Hz@10 MHz phase noise at 20.1 GHz carrier frequency, 4.9 mW DC power, and −193.3 dB figure-of-merit.

A 0.7-mW LC Voltage-Controlled Oscillator Leveraging Switched Biasing Technique for Low Phase Noise

A 0.8-V low-phase-noise voltage-controlled oscillator (VCO) by using 0.18- ${\mu }\text{m}$ CMOS process was proposed for a 2-GHz sliding-IF receiver. A noise filtering technique is utilized to reduce the thermal noise. Moreover, a switched biasing technique with gate voltage controlling is introduced for further lowering the phase noise and power consumption. By using a 3-bit binary-weighted switched capacitor array, the proposed VCO can achieve wide frequency tuning range. The measured results show the phase noise at 1 MHz offset frequency from the carrier signal is −123 dBc/Hz. The frequency tuning range is from 1.28 to 1.53 GHz. The power consumption is lower than 0.7 mW. The figure of merit is −193 dB.

Sub‐mW cognitive CMOS frequency down‐converter for internet of things

In this study, a suitable sub-mW frequency down converter for internet of things is presented. It is based on a single balanced switched transconductance mixer driven by a current-reuse LC voltage controlled oscillator (LC-VCO). For cognitive radio demonstration, the frequency converter is implemented with a tunable low-noise amplifier (LNA) in 0.13 µm standard complementary metal oxide semiconductor (CMOS) technology. Post-layout simulations return a gain conversion of 27 dB with a single-sideband noise figure of 8 dB (LNA included) for a consumption of 0.97 mW under a voltage supply of 1.2 V and an active area of 0.4 mm2. The stand-alone LC-VCO prototype exhibits a measured phase noise of −102 dBc/Hz at 1 MHz offset while showing −114 dBc/Hz in the post-layout simulation. The LC-VCO measured power consumption is only 260 µW from 1 V voltage supply with an active area of 0.173 mm2.