A 17.6-to-24.3 GHz −193.3 dB figure-of-merit LC voltage-controlled oscillator using layout floorplan optimization technique for Q-factor enhancement

Abstract

This paper presents a 20 GHz low-phase-noise low-power LC voltage-controlled oscillator (VCO). It adopts a fully differential tuning varactor, a coarse and a fine capacitor array to cover wide tuning range with a small tuning gain to reduce the amplitude-to-phase noise conversion. A layout floorplan is proposed to reduce the impact of the parasitic resistance of the interconnect and thus improve the Q of the LC tank in the VCO. Hence, the phase noise can be reduced without increasing power consumption. Post-layout simulation results show that the VCO with the proposed layout floorplan can get the phase noise reduction from 1.6 to 3.3 dB compared to the VCO with other layout floorplans in the case of the same power consumption. Implemented in a 65 nm CMOS process, the prototype achieves 17.6–24.3 GHz frequency range, −124 dBc/Hz@10 MHz phase noise at 20.1 GHz carrier frequency, 4.9 mW DC power, and −193.3 dB figure-of-merit.