LC VCO Research Articles

High data rate and energy efficient configurable IR-UWB transmitter with an integrated balun

This paper presents a novel, digitally configurable, switching oscillator-based impulse radio ultra-wideband (IR-UWB) transmitter that is robust to process variations. The pulse width and pulse position properties of the output waveform are configurable to ensure operation for the desired bandwidth and output pulse energy values. The architecture is based on a cross-coupled LC voltage-controlled oscillator (LC VCO) implemented with a custom-designed on-chip balun at a center frequency of 2.4 GHz. With the usage of this on-chip balun, the need for an extra buffer stage is eliminated, and the highest possible efficiency is achieved with the proper turns ratio selected. The generated digital control pulse signals are also used to ensure fast start-up and UWB operation while maintaining low power consumption with an implemented on/off tail switching scheme. The presented IR-UWB transmitter that occupies a total area of 0.35 mm2 is fabricated in the United Microelectronics Corporation (UMC) 180-nm mixed-mode/radio frequency (RF) CMOS process. The measured output voltage swing of the fabricated transmitter is 0.812 V on a 50-Ω load for the 200 Mb/s data rate, and the bandwidth is measured as 902 MHz. The achieved frequency tuning range is 1 GHz and the fabricated transmitter can drive 50 Ω, 75 Ω and 100 Ω loads with measured efficiency values 4.16%, 5.76%, and 4.05%, respectively. Compared to other works in the literature, this design achieves a higher output pulse energy at a higher data rate while maintaining low power consumption and, thus, high efficiency.

Ultrawideband Frequency Synthesis Using the Compact Tunable Transmission Line (CTTL)

Due to the rapid adoption of mmW bands for 5G communications, the complexity of transceiver systems must increase to operate over ever further separated frequency bands. In more traditional sub-6-GHz bands, software-defined radio (SDR) techniques allow for unified, multiband RF front ends; however, maintaining this ultrawideband or ultrawide tunable operation at mmW frequencies poses many challenges. One such challenge is ultrawideband mmW frequency synthesis, a challenge for which we present a new lumped/distributed tunable LC structure, the compact tunable transmission line (CTTL). In this article, we observe how the CTTL enables a state-of-the-art −203-dBc/Hz FOM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula> multioctave tunable mmW VCO, achieving a >4 octave tuning range with output up to 51 GHz. To analyze the CTTL in comparison to conventional tunable LC VCOs, we develop a new phase noise and oscillator figure-of-merit (FOM) model that provides an analysis framework for wide LC tuning. This new model is verified against simulation for conventional tuning and then is used to show how the CTTL provides a higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> and, therefore, better oscillator performance compared with existing LC tuning methods in the case of multioctave frequency synthesis. This analysis is then confirmed by the measured results of the manufactured CTTL VCO.

A 5.67-8.75GHz LC VCO with small gain variation for 2.4GHz-band WLAN applications

A 5.67-8.75GHz LC VCO with small gain variation for 2.4GHz-band WLAN applications

An Ultralow-Power Current-Reused Direct-Conversion Bluetooth-Low-Energy Receiver Front-End in 40-nm CMOS

An ultralow-power direct-conversion Bluetooth-low-energy (BLE) receiver (RX) front-end that employs current-reuse and subthreshold techniques is presented. A stacked and self-biased low-noise amplifier (LNA) with active balun consumes 400 μW and achieves a noise figure (NF) of 3.2-dB and a high gain (programmable from 18 to 31 dB), meeting the system specifications over the process, supply voltage, and temperature (PVT) variations. The RX front-end has a measured integrated NF of 5.2 dB from 50 KHz to 1 MHz that corresponds to a sensitivity of -95.1 dBm. At an RX gain of 47 dB, IIP3 was measured at -19.7 dBm. The LC VCO operates at twice the carrier frequency with a tuning range of 4.55 to 5.15 GHz in an integer-N phase-locked loop (PLL). An ultralow-power CML divider is used to generate the LO I/Q. The integrated phase noise (IPN) of the LO at 2.4 GHz is 0.83° with spot phase noise of -119.9 dBc/Hz at 3 MHz frequency offset. The PLL is entirely placed inside the VCO inductor resulting in an overall die area reduction of 8%. A 6- μW automatic dc offset-calibrator avoids saturation of consecutive baseband blocks. Multiple μW-level feedback control loops are used in the design to make it robust over PVT variations. The RX front-end prototype is implemented in a 40-nm LP CMOS process and occupies a silicon area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

BISH–QVCO: A Low–Power, Low–Phase noise Bulk–Injected Super–Harmonic coupling QVCO

In this paper, a novel method of Super–Harmonic coupling is proposed to generate quadrature outputs. In this method, by direct connection of all switching transistors bulk terminals, a second harmonic current is injected from each one of the I/Q oscillators to the other. Therefore, the proposed circuit is called Body–Injected Super–Harmonic coupling (BISH–) QVCO. The quadrature operation of the proposed circuit is mathematically proven and certified by simulations. In addition, through a detailed analysis, closed–form expressions are derived for the output phase noise and phase error. To have a fair performance evaluation of the proposed topology, the proposed BISH-QVCO, and the conventional P–QVCO are designed and simulated in 0.18 ​μm RF-CMOS technology with 3.22–3.64 ​GHz oscillation frequency (12.25% tuning range), a power supply of 1.8V, and the same power consumption of 3.85 ​mW. The quality factor of the tank circuits is calculated as 9.2. Post layout simulation results predict phase noise of −122.3dBc/Hz at 1 ​MHz offset from 3.64 ​GHz oscillation frequency that presents 4.1 ​dB and 2.7 ​dB phase noise improvements compared to the conventional P–QVCO and simple LC VCO, respectively. The maximum I and Q outputs phase error due to a 2% tank capacitor mismatch is 7°. A FOMT of 189.4 ​dB is achieved for the proposed QVCO. Also, the proposed method is capable of generating multi–phase outputs, which can be ranked among the well-performing ones.

A Wideband Fast Start-Up Multi-Core VCO With Auto-Frequency Control in 0.18 μm CMOS

A 2.8 – 4.6 GHz wideband multi-core VCO with a fast start-up scheme is presented in this brief. The proposed multi-core VCO uses a successive approximation register based auto frequency control (SAR-AFC) loop with the embedded 2/3 Judge to ensure the desired output frequency. To benefit a wider application, the VCO provides radio and low frequency outputs. A prototype of the multi-core VCO is implemented in 180-nm CMOS, and consumes 20 mA from a 3.3-V supply voltage with an active area of 4.8 mm2. Measured results indicate that the multi-core LC VCO is capable of providing the phase noise of −120 dBc/Hz at 1-MHz offset from 4.6 GHz frequency. One of the attractive merits from the proposed LC VCO is that the response time could be saved 45% over the traditional VCO architecture.

A comparative study between Class-C and Class-B quadrature voltage-controlled power oscillator for multi-standard applications

In this paper a 0.35 ​mW Class-C/B series coupling quadrature voltage-controlled power oscillator (S-QVCO) based on the coupling between two identical LC VCOs is presented. The S-QVCO is designed using a 130 ​nm CMOS technology and it is suitable for multi-standard applications. High quality factor inductor is designed using the two top metal layers to enhance the phase noise performance of the VCO, also an improved switching varactor is used to achieve dual bands. The proposed QVCO achieves tuning range of 28.2% from 2.3 to 3.07 ​GHz, and low phase noise of −119.2 dBc at a 1-MHz offset frequency from 2.7 ​GHz carrier. By biasing the proposed QVCO in class-C, the DC current is reduced to 0.35 ​mA compared to 1.48 ​mA in class-B from 1 ​V supply voltage. The minimum achieved Figure-of-Merit (FOM) equals −192 dBc/Hz and the maximum given output power is 6.5 dBm. The phase error between quadrature output signals is maximum of 0.25° . The occupied area of the proposed QVCO equals0.34mm2, while the total chip area including RF pads is1mm2.

A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation

This work presents the design of a new and unique design technique of constant loop bandwidth and phase-noise cancellation in a wideband ΔΣ fractional-N PLL frequency synthesizer. Phase noise performance of the proposed ΔΣ fractional-N PLL frequency synthesizer has been verified using CppSim simulator with the help of transistor level simulation results in Cadence SpecctreRF. Transient response of the proposed ΔΣ fractional-N PLL has been verified in transistor level simulation using Cadence SpectreRF in 0.13 μm standard CMOS process. The proposed phase-noise cancellation and constant loop bandwidth in wideband ΔΣ fractional-N PLL reduces the out of band phase noise by 18 dBc/Hz at 2 MHz offset frequency for a closed loop bandwidth of 1 MHz, when ICP,max is equal to 2.6 mA. PLL locking time has been reduced with phase-noise cancellation and a constant loop bandwidth calibration circuits using the proposed CP unit current cell for the mismatch compensated PFD/DAC in wideband ΔΣ fractional-N PLL frequency synthesizer. Optimum phase noise performance can be achieved with the help of proposed design technique. Proposed ΔΣ fractional-N PLL frequency synthesizer is locked within 14.0 μs with an automatic frequency control circuit of the LC VCO and a constant loop bandwidth calibration circuit through the use of proposed CP unit current cell for the mismatch compensated PFD/DAC for the phase-noise cancellation in worst case condition of KVFC = 10 and KLBC = 150. Our new design technique can be extensively integrated for wideband fractional-N PLL for new type of wireless communication paradigm using the thinnest channel subharmonic transistor and low power devices, and it has the potential to open a new era of fractional-N PLLs for wideband application.

Wood receives FEED contract from IRPC for ‘world-scale’ Thai paraxylene plant

This work presents the design of an automatic frequency and amplitude control LC VCO circuit with noise filtering technique for fractional-N PLL frequency synthesizers. The LC VCO frequency of operation is from 2.158 GHz to 5.133 GHz. Phase noise of the LC VCO at 1 MHz offset frequency is −123.0 dBc/Hz and −116.8 dBc/Hz for carrier signal frequency of 2.158 GHz and 5.133 GHz, respectively. The power consumption of the LC VCO without buffer circuit is 5.14 mW from a 1.2 V power supply and the fractional-N PLL has been implemented in 0.13 μm standard CMOS process. A binary search fast frequency calibration process greatly reduces the overall locking time of the fractional-N PLL frequency synthesizers along with proposed PFD and a CP switching circuit and an efficient pulse swallow based fractional divider circuits, fractional bits are controlled by the HK-MASH 111 Digital Delta Sigma Modulator (DDSM). The fractional-N PLL is coarsely tuned within the maximum time of 1.825 μs and the fractional-N PLL is locked within 4 μs considering the worst case coarse tuning condition.

A low phase noise multi-band LC VCO using a switched differential inductor

A low phase noise multi-band LC VCO using a switched differential inductor

Fast Startup of LC VCOs Using Circuit Asymmetries

An LC VCO whose design includes deliberate circuit mismatches is presented. It is shown that such mismatches can reduce the oscillation start-up time due to a common-mode disturbance simultaneous with the turn-on of the tail current. The use of this technique is applied to a low-power transmitter for an ultra-wideband wireless communication system using the on–off keying modulation scheme. Measurements using a 0.18- ${\mu }\text{m}$ CMOS technology with a 4.2-GHz carrier frequency demonstrate the technique.

Self‐biased CMOS LC VCO based on trans‐conductance linearisation technique

Self‐biased CMOS LC VCO based on trans‐conductance linearisation technique

Low phase noise LC VCO with sinusoidal tail current shaping using cascode current source

Tail current shaping is a known technique for phase noise reduction. According to this technique, close to outputs zero crossing points, where Impulse Sensitivity Function (ISF) is maximum, current supplying path to the transistor pair is disconnected. In this paper, tail current shaping is performed by two additional transistors that are placed in cascode configuration with the tail current source. Conventional tail current shaping is performed by two tail transistors with the gates connected to the oscillator outputs. The proposed circuit outperforms the conventional circuit in phase noise performance, due to four mechanisms: higher impedance seen from the common source of switching transistors due to cascode current source; better tail current shaping; higher oscillation amplitude with the same power consumption; and lower RMS value of the effective ISF. Also, the proposed circuit presents more stable bias point and output amplitude, compared to conventional circuit. In addition, higher ratio of start-up tail current to the minimum of shaped tail current for the proposed circuit, removes the need for additional start-up detection circuits. Post layout simulations predict a sample oscillator designed at 4GHz in 0.18µm RF CMOS technology presents 11.3 and 3.8dB less phase noise at 1MHz offset, compared to simple and conventional oscillators, respectively.

Design of LC VCO With Current Mirror using 180 Nm Technology with Improved Power and Phase Noise

Design of LC VCO With Current Mirror using 180 Nm Technology with Improved Power and Phase Noise

A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process

A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process

A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in [formula omitted] fractional-N PLL frequency synthesizer

This work presents the design of a ΔΣ fractional-N PLL frequency synthesizer with a new loop bandwidth calibration and automatic frequency control (AFC) circuit, applicable for wide band RF communication system. This new and unique loop bandwidth calibration circuit has been implemented using logarithmic and anti-logarithmic (Base2) architecture. This architecture is an efficient design technique as well as faster operation in CMOS domain. The operating frequency range of the ΔΣ fractional-N PLL frequency synthesizer is from 2.158 to 5.133GHz. The variation of LC VCO gain (KVCO) is obvious due to wide band application and it varies from 30.65MHz/Volt to 368MHz/Volt for the frequency range of 2.158–5.133GHz. Constant loop bandwidth is maintained by controlling the charge pump current. Power consumption of the ΔΣ fractional-N PLL frequency synthesizer is 34mW from a 1.2Volt power supply and the work has been carried out in 0.13μm standard CMOS process. Also, this design includes an automatic frequency control unit for the LC VCO circuit which is coarsely tuned within 1.825μs for KVFC=10 for worst case condition and it completes the loop bandwidth (LBW) calibration within 7.84μs for KLBC=150 for worst case condition. The maximum locking time of the ΔΣ fractional-N PLL frequency synthesizer with loop bandwidth calibration and automatic frequency control circuit is 12.7μs for KVFC=10 and KLBC=150 for worst case condition. The ΔΣ fractional-N PLL is locked much faster than any work reported earlier using the proposed PFD, CP, proposed pulse swallow divider, efficient AFC circuit for LC VCO and a new loop BW calibration technique in transistor level simulation using Cadence SpectreRF. The main advantage of this loop bandwidth calibration technique is that the calibration time can be adjusted according to the PLL output frequency, loop bandwidth calibration accuracy and tuning frequency range of the LC VCO.

A high‐efficiency 60‐GHz indirect local oscillator in 90‐nm CMOS

ABSTRACTThis letter presents a highly efficient 60‐GHz local oscillator (LO) in a 90‐nm CMOS. The proposed LO consists a 30‐GHz LC VCO and a frequency doubler. With this topology, the LO generator has a high output power of −0.1 dBm at 58.2 GHz, consuming only 10.4 mW from a 0.8 V supply, resulting in a record efficiency of 9.4% among 60‐GHz CMOS LOs. At 58.2 GHz, the phase noise is −115 dBc/Hz at a 10‐MHz offset. The measured frequency tuning range is from 57.56 to 64.47 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2091–2093, 2016

A fast automatic frequency and amplitude control LC-VCO circuit with noise filtering technique for a fractional-N PLL frequency synthesizer

This work presents the design of an automatic frequency and amplitude control LC VCO circuit with noise filtering technique for fractional-N PLL frequency synthesizers. The LC VCO frequency of operation is from 2.158GHz to 5.133GHz. Phase noise of the LC VCO at 1MHz offset frequency is −123.0dBc/Hz and −116.8dBc/Hz for carrier signal frequency of 2.158GHz and 5.133GHz, respectively. The power consumption of the LC VCO without buffer circuit is 5.14mW from a 1.2V power supply and the fractional-N PLL has been implemented in 0.13μm standard CMOS process. A binary search fast frequency calibration process greatly reduces the overall locking time of the fractional-N PLL frequency synthesizers along with proposed PFD and a CP switching circuit and an efficient pulse swallow based fractional divider circuits, fractional bits are controlled by the HK-MASH 111 Digital Delta Sigma Modulator (DDSM). The fractional-N PLL is coarsely tuned within the maximum time of 1.825μs and the fractional-N PLL is locked within 4μs considering the worst case coarse tuning condition.

Understanding Phase Noise in LC VCOs: A Key Problem in RF Integrated Circuits

The design of low-phase-noise inductorcapacitor voltage-controlled oscillators (LC VCOs) has been one of the most important topics in the field of radio frequency (RF) integrated circuits in last 20 years. A huge number of IEEE papers have been devoted to this subject, which is quite a unique circumstance for a circuit that typically embeds from three (sometimes two) to five transistors. The reasons for this widespread interest are well known, i.e., the phase noise of VCOs is one major obstacle encountered during the design of RF transceivers, and the power dissipated to meet the noise specs is often a nonnegligible portion of the total budget. A second reason is the intrinsic time-variant nature (often also nonlinear) of these circuits, which makes their analysis very difficult

Design of SET tolerant LC oscillators using distributed bias circuitry

In this paper, a distributed biasing technique is proposed to improve the single event transient (SET) tolerance in LC-tank voltage controlled oscillators. The charge generated by a radiation strike at the drain of the bias current transistor results in voltage change at the drain node, which causes change in the output impedance of the transistor. This effect is more pronounced in the case of distributed biasing, and is used for improving the SET tolerance in the oscillator. Circuit simulations show that the phase error introduced due to a radiation strike is reduced to one-third in a 14GHz LC–VCO designed in a standard 90nm CMOS technology when the distributed bias is used, as compared to the phase error in a conventional LC–VCO.