Fast Startup of LC VCOs Using Circuit Asymmetries

Abstract

An LC VCO whose design includes deliberate circuit mismatches is presented. It is shown that such mismatches can reduce the oscillation start-up time due to a common-mode disturbance simultaneous with the turn-on of the tail current. The use of this technique is applied to a low-power transmitter for an ultra-wideband wireless communication system using the on–off keying modulation scheme. Measurements using a 0.18- ${\mu }\text{m}$ CMOS technology with a 4.2-GHz carrier frequency demonstrate the technique.