Abstract
A 2.8 – 4.6 GHz wideband multi-core VCO with a fast start-up scheme is presented in this brief. The proposed multi-core VCO uses a successive approximation register based auto frequency control (SAR-AFC) loop with the embedded 2/3 Judge to ensure the desired output frequency. To benefit a wider application, the VCO provides radio and low frequency outputs. A prototype of the multi-core VCO is implemented in 180-nm CMOS, and consumes 20 mA from a 3.3-V supply voltage with an active area of 4.8 mm2. Measured results indicate that the multi-core LC VCO is capable of providing the phase noise of −120 dBc/Hz at 1-MHz offset from 4.6 GHz frequency. One of the attractive merits from the proposed LC VCO is that the response time could be saved 45% over the traditional VCO architecture.
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