LC-tank Voltage-controlled Oscillator Research Articles

A fully integrated nanosecond burst RF generator for quantum technologies

AbstractQuantum technologies is an emerging field of physics and engineering based on exploiting properties of quantum mechanics such as entanglement, superposition, or tunneling, and which is expected to impact many applications, such as communications, simulation, computation, or sensing and metrology. The operation of quantum technologies is based on the manipulation of the quantum states of certain devices, either to induce transitions between states or to detect the transitions. Irrespective of the practical realization of these quantum devices, their manipulation requires interacting with their quantum resonant states, for which very narrow radio‐frequency (RF) bursts in the range of the GHz are required. Arbitrary waveform generators are used to generate these signals for test purposes, but this is not suitable for practical quantum technology applications, which will need to produce the required bursts by specific circuit building blocks with low power and small dimensions. Here, an integrated RF burst generator capable of producing GHz bursts shorter than 1 ns is presented. The proposed architecture is tested using a 5 GHz quadrature LC‐tank voltage‐controlled oscillator (LC‐VCO), showing that the four equally spaced phases can be switched every 500 ps, which allows the generation of more complex RF bursts for optimized quantum state manipulation.

A Ku-Band Voltage-Controlled Oscillator Equipped With a Compact Enhanced Linearity Tuning Converter

This letter proposes a Ku-band LC-tank voltage-controlled oscillator (VCO) equipped with a compact enhanced linearity tuning converter, which was fabricated using the 0.18-μm CMOS process of Taiwan Semiconductor Manufacturing Company (TSMC). The proposed linearity tuning converter dissipated only a few 10-μA currents and compensated for the nonlinearity of the resonant tank, ensuring the linearity tuning characteristic of the VCO. A small tuning sensitivity variation of 80-280 MHz/V was attained at operating frequencies from 13.2 to 14.7 GHz. The measured phase noise was -114.9 dBc/Hz at a 1-MHz offset frequency from the carrier signal of 13.5 GHz. The chip size, including the linearity tuning converter, was 0.7×0.93 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The proposed VCO with a supply voltage of 1.8 V dissipated a current of 4 mA.

A Low Phase Noise, High Phase Accuracy Quadrature LC-VCO With Dual-Tail Current Biasing to Insert Reconfigurable Phase Delay

This brief presents a novel low phase noise and low phase error quadrature LC-tank voltage controlled oscillator (LC-VCO), which utilizes the dual-tail current biasing technique to insert a phase shift in the coupling path. The dual-tail current bias each oscillation branch, and are gated by quadrature signals. One tail current, named coupling-tail current, is gated by the quadrature phase signal to force the voltage controlled oscillator to keep quadrature state. The other tail current, named self-tail current, is gated by the anti-phase signal to introduce a phase shift in total bias current. The phase shift is reconfigurable by adjusting the DC biasing voltage of tail current transistors to resist the performance deterioration caused by process variations. Compared with the conventional quadrature LC-VCO, the proposed quadrature LC-VCO enhances the phase accuracy and optimize the phase noise simultaneously. Additionally, it has the distinct advantage of reconfigurability. The core was fabricated in 180 nm 1P6M CMOS process, and occupied a die area of 0.96 mm2 totally. The measurement results show it achieves a phase noise of −129.3 dBc/Hz @1 MHz offset and a phase error of 0.09° while $k=0.4$ , $V_{\mathrm {b0}}= 0.8$ V, and $V_{\mathrm {b1}}= 0.6$ V @2.5 GHz. The total power consumption is 20.6 mW with a supply voltage of 1.8 V.

A 30-GHz Power-Efficient PLL Frequency Synthesizer for 60-GHz Applications

This paper presents the design and verification of a proposed 30-GHz power-efficient phase-locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a commercial 0.18- $\mu \text{m}$ SiGe BiCMOS process, the synthesizer employs coupled LC tank voltage-controlled oscillator, high power-added efficiency amplifier, reconfigurable divider realizing fractional division ratios for choice of multiple reference frequencies and low operation power, a programmable charge pump, an internal loop filter, and an integrated slave serial peripheral interface. The PLL synthesizer (PLLS) provides output frequency from 29.5 to 33.4 GHz with phase noise of −97 dBc/Hz at 1-MHz offset. The integrated phase noise over the frequency of 10 kHz–10 MHz is 2.05° rms at a frequency of 30.24 GHz. Operating with a single 1.8-V supply voltage, the PLLS consumes a low power of 63 mW and occupies an area of 2.8 mm $\times$ 1.86 mm.

Analysis and Design of Digital Controlled Low-Phase-Noise CMOS LC_VCO

A fully integrated cross-coupled digital controlled LC tank voltage-controlled oscillator (LC-VCO) is proposed to achieve a low phase noise, the LC_VCO receives the external n-bits control words FTRIM to control the capacitors switches and change LC-tank shunt capacitors, thus changes the tuning range of LC_VCO. Meanwhile the LC_VCO receives the external k-bits control words KVCO to control the varactors switches and led to the change of voltage control sensitivity. The digital controlled oscillator based on the proposed topology is simulated and verified by the standard SMIC 0.13um CMOS technology. The simulation gave a phase noise of -125.3dBc/Hz at 1 MHz, the entire circuit consumes the current is only 2.98mA under a 1.2 V supply.

8-GHz, 6.6-mW LC-VCO with Small Die Area and FOM of 204 dBc/Hz at 1-MHz Offset

This letter discusses the design of an 8-GHz LC-tank voltage-controlled oscillator (VCO) for use in a receiver chain developed for the Cerro Chajnantor Atacama Telescope Heterodyne Array Instrument. A VCO-optimization approach is proposed that reduces the phase noise (PN) and minimizes the VCO die area. An LC-VCO is realized in a 0.13- $ {\mu }\text {m}$ CMOS technology to validate the design methodology experimentally. The VCO achieves a worst-case PN, within the whole tuning range of 850 MHz, of -131 dBc/Hz at a 1-MHz offset. At 8 GHz the oscillator PN is measured to be -134.3 dBc/Hz at a 1-MHz offset achieving a figure of merit (FOM) of 204 dBc/Hz.

Clock and Data Recovery for 10-Gb/s EPON Application

An integrated 10-Gb/s clock and data recovery circuit incorporates a LC-tank voltage-controlled oscillator, a half-rate binary phase detector and charge pump. On the basis of R.C.Walker's second-order model, and in accordance with jitter tolerance and jitter transfer, the minimum stability factor are derived in a view to determine the value of Cz and Rz finally. Accomplished circuit design in 0.13-um CMOS process, the power consumption is 210 mW from a supply voltage of 1.2V. When 10.125 Gb/s pseudorandom binary sequence is used, the jitter of the recovered clock is a peak-to- peak jitter of 8 ps.

A Wideband Gain Linearized Microwave Voltage Controlled Oscillator with Low Phase Noise Variation in Nanometer CMOS Technology

A wideband CMOS LC tank voltage-controlled oscillator (VCO) with low phase noise variations and a linearized gain has been designed using a new binary-weighted switched-capacitor and digitally-controlled varactor bank. The novel design has the advantages of more linear VCO frequency tuning, lower phase noise and reduced gain to variations in supply voltage. The proposed VCO has been designed using UMC 90-nm, 6-metal CMOS technology and features phase noise variation of less than 4.9 dBc/Hz. The VCO operates from 3.45 to 6.55 GHz, with phase noise of -133.4 dBc/Hz at a 1 MHz offset, a figure of merit (FoM) of -203.3 dBc/Hz, less than 41 dBm spurious harmonics, and a total VCO core current consumption of 1.18 mA from a 3.3 V voltage supply. To the authors' knowledge, this is the lowest phase noise variation ever reported.

Triple-Band Transformer-Coupled LC Oscillator With Large Output Voltage Swing

This letter presents a low phase noise triple-band voltage-controlled oscillator (VCO). The designed circuit consists of a dual-resonance LC-tank VCO and a single-resonance LC-tank VCO. The two sub-VCOs are coupled via transformers and varactors. The net LC resonator has three main resonant frequencies selectable by controlling the bias of varactors. The proposed VCO has been fabricated with the TSMC 0.18 $\mu$ m 1P6M CMOS technology. The VCO can generate differential signals in the frequency range of 2.80–3.57, 7.43–7.65, and 8.23–8.77 GHz with core power consumption of 3.3, 4, and 4.2 mW at the dc drain-source bias of 0.65 V, respectively. At 3.49, 7.53, and 8.52 GHz phase noises at 1 MHz offset are ${-}123.06$ dBc/GHz, ${-}119.62$ dBc/Hz, and ${-}118.34$ dBc/Hz, respectively. The die area of the triple-band VCO is 0.626 $\, \times \,$ 0.912 mm $^{2}$ .

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- $$\upmu \hbox {m}$$ μ m CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of $$-$$ - 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only $$594~\upmu \hbox {W}$$ 594 μ W in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is $$-$$ - 192.1 dB at 3 GHz.

Ultra-Low Power, Low Phase Noise 10 GHz LC VCO in the Subthreshold Regime

A new design for an ultra-low power, low phase noise differential 10 GHz LC voltage-controlled oscillator (VCO) which is biased in the subthreshold regime, is presented in the 0.18 μm CMOS process, for the first time. The designed circuit topology is an NMOS only cross-coupled LC-tank VCO which has an extra symmetric centre tapped inductor between the source ends of the cross-coupled transistors. Using this inductor leads to an improvement of the phase noise of VCO about 3.5 dB. At the supply voltage of 0.46 V, the output phase noise is －107.8 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 10.53 GHz, so that the dc power consumption is only 0.346 mW. Tuning range is between 10.53 GHz to 11.35 GHz which is 7.5% and the figure of merit is －193.8 dB, which this result shows that this is the first VCO design in the subthreshold regime at this frequency. This VCO can be used for multi-standard wireless LAN communication protocols 802.11a/b/g easily by a frequency division of 2 or 4 respectively.

A LOW POWER LOW PHASE NOISE LC VOLTAGE-CONTROLLED OSCILLATOR

A low phase noise CMOS complementary cross-coupled LC-tank voltage-controlled oscillator (VCO), implemented with TSMC 0.18μm 1P6M CMOS technology, is presented. Double pair pseudoresistance transistors biased by the tapped center of the inductor are utilized to reduce the DC bias current. The circuit consumes 1.55 mA from a 1.5 V supply voltage which saves up to 52.4% power, compared with the conventional one. Furthermore, an adaptive body biasing technique (ABB) is used to overcome the effect of PVT variations. The VCO is tunable from 2.58 to 3.07 GHz and has a phase noise −122.7 dBc/Hz at 1 MHz offset from the 3 GHz carrier. The Figure of Merit (FOM) of the proposed VCO is −188.8 dBc, and the figure of merit including the tuning range (FOMT ) is −193.5 dBc.

A 21.68 GHz low-power frequency synthesizer chip design with an injection-locked frequency divider

A 21.68 GHz low-power frequency synthesizer with a LC-tank voltage-controlled oscillator (VCO) is implemented in TSMC 90 nm CMOS process.In this proposed circuit, there are three important features. The primary advantage of this circuit is the use of an all-NMOS cross-coupled Colpitts VCO, which decreases transistor parasitic capacitances and reduces phase noise. Second, an injection-locked frequency divider (ILFD) is utilized in the first divider stage to divide the high frequency signal. Third, a low supply voltage of 1.2 V is used to reduce power consumption. Measured results achieve that the locked output frequency is tunable from 21.54–21.96 GHz and the phase noise is about −97.47 dBc/Hz at 1 MHz offset from 21.68 GHz. The mixed output power spectrum at ILFD output frequency of 10.22 GHz is −2.97 dBm and the overall power consumption is 9.24 mW. Including pads, the chip area is 0.8 (0.8 × 1.0) mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:200–205, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27229

Dual-band low-phase-noise LC-QVCO using series coupling and switched biasing techniques

An LC-tank quadrature voltage-controlled oscillator (QVCO) is proposed to achieve frequency-band reconfigurability and low phase noise. In this work, phase noise contributed by the 1/f noise of coupling transistors and tail transistors is noticeably reduced when series coupling and switched biasing techniques are simultaneously adopted. The proposed QVCO was implemented in 0.25-μm triple-well CMOS process for K-PCS and WCDMA bands. Measured results showed a phase noise of −117 dBc/Hz at an offset of 1 MHz and a phase-noise figure-of-merit of −172 dBc/Hz while consuming 8.13 mA from a 2-V power supply.

Simulation and Realization of MOS Varactors

MOS varactors have been used commonly as tuning components in LC-tank voltage-controlled oscillators (VCOs) based on standard CMOS technology. MOS varactor topologies include traditional D=S=B structure, inversion-mode (I-MOS) structure and accumulation- mode (A-MOS) structure. A novel simulation method of the three MOS varactors is proposed. The A-MOS structures are implemented by developed models, which are based on sub-circuits utilizing BSIM3v3 models. Simulation results show that the I-MOS and A-MOS varactors has a wider tuning range than the D=S=B varactor. Three MOS varactors are implemented in CSMC 0.5um CMOS technology.

A 33% tuning range voltage-controlled oscillator robust to environmental variation

A low-voltage differential voltage-controlled oscillator (VCO) is designed and implemented in a 90-nm CMOS 1P9M process.The designed circuit topology is an nMOS-core cross-coupled LC-tank VCO robust to process, voltage and temperature variation. At the supply voltage of 0.4 V, the output phase noise of the VCO is −108.78 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 10.13 GHz, and the figure of merit is −187.68 dBc/Hz. The power consumption is 1.32 mW. Tuning range is about 3.62 GHz, from 9.15 to 12.77 GHz, while the control voltage was tuned from 0 to 1.0 V. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:517–519, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25775

Design and realization of an ultra-low-power low-phase-noise CMOS LC-VCO

A fully integrated cross-coupled LC tank voltage-controlled oscillator (LC-VCO) using transformer feedback is proposed to achieve a low phase noise and ultra-low-power design even at a supply below the threshold voltage. The ultra-low-power VCO is implemented in the mixed-signal and RF 1P6M 0.18-μm CMOS technology of SMIC. The measured phase noise is −125.3 dBc/Hz at an offset frequency of 1 MHz from a carrier of 2.433 GHz, while the VCO core circuit draws only 640 μW from a 0.4-V supply. The designed VCO can cover a frequency range from 2.28 to 2.48 GHz. The tuning range of the circuit is 200 MHz (8.7%) and the FOM is −195.7 dB, which is suitable for an IEEE 802.11b receiver.

Colpitts VCO with gate-series high-quality factor LC resonator

A new differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13-μm CMOS 1P8M process. The designed circuit topology is an n-core LC-tank VCO with an LC resonator. At the supply voltage of 1.1 V, the output phase noise of the VCO is −113.8 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 11.73 GHz and the figure of merit is −192.01 dBc/Hz. The core power consumption is 1.83 mW. Tuning range is 1.47 GHz from 10.66 to 12.13 GHz, while the control voltage was tuned from 0 to 1.2 V. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2170–2173, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25466

A Δ-Σ fractional-N frequency synthesiser with quantisation noise folding suppression

A wideband Δ-Σ fractional-N frequency synthesiser with novel Δ-Σ quantisation noise folding suppression technique is presented in this article. A novel linearisation technique is proposed to suppress Δ-Σ quantisation noise folding due to nonlinearity of the phase frequency detector/charge pump (PFD/CP). In order to cover a wide frequency band and process, voltage and temperature (PVT) variation, a switched capacitors LC tank voltage-controlled oscillator and closed-loop automatic frequency band selection method are adopted. The chip is fabricated in a HeJian 0.18 radio frequency (RF) CMOS process. The measured output frequency is from 1.75 to 2.25 GHz with tuning range as wide as 500 MHz. The measured phase noise performance is −81.97 dBc/Hz and −112 dBc/Hz at 10-KHz and 1-MHz offset frequency, respectively. The measured reference spur is −44.05 dBc/Hz at 10-MHz offset frequency. The frequency synthesiser consumes 27.8 mW from a 1.8 V power supply.

A 0.3 V Cross-Coupled VCO Using Dynamic Threshold MOSFET

An ultra-low voltage differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 ? m CMOS 1P8M process. The designed circuit topology is an nMOS-core cross-coupled LC-tank VCO, and a self-generated 2nd harmonic ac signal is coupled to the bodies of MOSFETs to enhance the VCO performance. At the supply voltage of 0.3 V, the output phase noise of the VCO is -116.88 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 3.579 GHz, and the figure of merit is -194.43 dBc/Hz. Total power consumption is 0.225 mW. Tuning range is about 240(770) MHz, from 3.39 to 3.63(4.16) GHz, while the control voltage was tuned from 0 V to 0.3(1.0) V.