A 21.68 GHz low-power frequency synthesizer chip design with an injection-locked frequency divider

Abstract

A 21.68 GHz low-power frequency synthesizer with a LC-tank voltage-controlled oscillator (VCO) is implemented in TSMC 90 nm CMOS process.In this proposed circuit, there are three important features. The primary advantage of this circuit is the use of an all-NMOS cross-coupled Colpitts VCO, which decreases transistor parasitic capacitances and reduces phase noise. Second, an injection-locked frequency divider (ILFD) is utilized in the first divider stage to divide the high frequency signal. Third, a low supply voltage of 1.2 V is used to reduce power consumption. Measured results achieve that the locked output frequency is tunable from 21.54–21.96 GHz and the phase noise is about −97.47 dBc/Hz at 1 MHz offset from 21.68 GHz. The mixed output power spectrum at ILFD output frequency of 10.22 GHz is −2.97 dBm and the overall power consumption is 9.24 mW. Including pads, the chip area is 0.8 (0.8 × 1.0) mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:200–205, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27229