A Δ-Σ fractional-N frequency synthesiser with quantisation noise folding suppression

Abstract

A wideband Δ-Σ fractional-N frequency synthesiser with novel Δ-Σ quantisation noise folding suppression technique is presented in this article. A novel linearisation technique is proposed to suppress Δ-Σ quantisation noise folding due to nonlinearity of the phase frequency detector/charge pump (PFD/CP). In order to cover a wide frequency band and process, voltage and temperature (PVT) variation, a switched capacitors LC tank voltage-controlled oscillator and closed-loop automatic frequency band selection method are adopted. The chip is fabricated in a HeJian 0.18 radio frequency (RF) CMOS process. The measured output frequency is from 1.75 to 2.25 GHz with tuning range as wide as 500 MHz. The measured phase noise performance is −81.97 dBc/Hz and −112 dBc/Hz at 10-KHz and 1-MHz offset frequency, respectively. The measured reference spur is −44.05 dBc/Hz at 10-MHz offset frequency. The frequency synthesiser consumes 27.8 mW from a 1.8 V power supply.