Laterally Diffused Metal-oxide-semiconductor Field-effect Transistor Research Articles

500 V breakdown voltage in β‐Ga2O3 laterally diffused metal‐oxide‐semiconductor field‐effect transistor with 108 MW/cm2 power figure of merit

AbstractThe authors’ present a silicon‐on‐insulator (SOI) laterally diffused metal‐oxide‐semiconductor field‐effect transistor (LDMOSFET) with β‐Ga2O3 , which is a large bandgap semiconductor (β‐LDMOSFET), for increasing breakdown voltage (VBR) and power figure of merit. The fundamental purpose is to use a β‐Ga2O3 semiconductor instead of silicon material due to its large breakdown field. The characteristics of β‐LDMOSFET are analysed to those of standard LDMOSFET, such as VBR, ON‐resistance (RON), power figure of merit (PFOM), and radio frequency (RF) performances. The effects of RF, such as gate‐drain capacitance (CGD), gate‐source capacitance (CGS), transit frequency (fT), and maximum frequency of oscillation (fMAX) have been investigated. The β‐LDMOSFET structure outperforms performance in the VBR by increasing it to 500 versus 84.4 V in standard LDMOSFET design. The suggested β‐LDMOSFET has RON ~ 2.3 mΩ.cm−2 and increased the PFOM (VBR2/RON) to 108.6 MW/cm2. All the simulations are done with TCAD and simulation models are calibrated with the experimental data.

Surrogate models for device design using sample-efficient Deep Learning

Generation of training dataset for machine learning-based device design algorithm is expensive. To address this, we propose an active learning approach. Its efficiency is demonstrated through a Deep Neural Network (DNN) based Laterally Diffused Metal Oxide Semiconductor Field-effect Transistor (LDMOSFET) off-state breakdown voltage (BVDS,off) and specific on-resistance (Rsp) predictor. Our results show the possibility of ∼50% reduction in the training dataset size without compromising the baseline accuracy. Specifically, we compared eight sampling techniques and found that Informative-Query by Committee (I-QBC) and Diverse Informative-Greedy Sampling (DI-GS) techniques work best with ∼1.87% Euclidean Norm of Prediction Error (ENPE).

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to silicon carbide (SiC). This novel silicon-on-silicon-carbide (Si/SiC) substrate solution promises to combine the benefits of silicon-on-insulator (SOI) technology (i.e device confinement, radiation tolerance, high and low temperature performance) with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance). Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

A New Self-Heat Modeling Approach for LDMOS Devices

The purpose of this research is to characterize and model the self-heating effect of n-channel Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistors (LDMOS). In order to improve the accuracy and convergence of the self-heating (SH) simulations in DC, transient and small signal AC (S-Parameter) domains, a new SH model has been developed and implemented in Verilog-A version of BSIM4 model to simulate an LDMOS device. The new SH model does not require a separate thermal network. It has been verified with measurements in static DC, transient, and small signal AC (S-parameter). Excellent agreements between measured and simulated results have been obtained without sacrificing simulation speed and convergence performance.

Performance optimization of InGaAs power LDMOSFET

In this paper, a power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on InGaAs is proposed to achieve substantial improvement in breakdown voltage, on-resistance and Baliga׳s figure-of-merit with reduced cell pitch. The proposed LDMOSFET contains two vertical gates which are placed in two separate trenches built in the drift region. The source and drain contacts are taken from the top. The modified device has a planer structure implemented on InGaAs which is suitable for medium voltage power integrated circuits. The performance of proposed device is evaluated using two-dimensional numerical simulations and results are compared with that of the conventional LDMOSFET. The proposed structure considerably reduces the electric field inside the drift region due to reduced-surface field (RESURF) effect even at increased doping concentration leading to improved design trade-off. The proposed device provides 144% higher breakdown voltage, 25% lower specific on-resistance, 8 times improvement in figure-of-merit, and 25% reduction in cell pitch as compared to the conventional device.

High figure-of-merit SOI power LDMOS for power integrated circuits

The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two separate trenches build in the drift region and single source and drain contacts are taken on the top. The trench structure reduces the electric field inside the drift region and allow increased drift layer doping concentration leading to higher breakdown voltage, lower specific on-resistance, reduced gate-drain charge, and substantial improvement in the figure-of-merits. Using two-dimensional simulations, the performance of the proposed LDMOS is optimized and results are compared with the conventional LDMOS. Our simulation results show that the proposed device exhibits 110% higher breakdown voltage, 40% reduction in cell pitch, 19% lower specific on-resistance, 30% lower gate-to-drain charge leading to 5.5 times improvement in Baliga's figure-of-merit and 43% reduction in dynamic figure-of-merit over the conventional device.

A dc model for partially depleted SOI laterally diffused MOSFETs utilizing the HiSIM-HV compact model

This paper presents a subcircuit compact model to study the dc characteristics of a partially depleted (PD) SOI laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) utilizing the HiSIM-HV compact model. Our model accounts both for the high-voltage and the floating-body effects such as the quasi saturation effect, the impact ionization in the drift region and the famous kink effect. The high-voltage effects, due to the surface MOS region of PD SOI LDMOSFET, are modeled using the HiSIM-HV model. The HiSIM-HV model, a surface-potential-based compact model, is used as a baseline model as it determines the potential consistently in the complete PD SOI LDMOSFET. And, to incorporate the floating-body effects into the HiSIM-HV model, we have used the same approach as used in developing BSIMSOI model. It is shown that to model the floating-body effects, mainly the kink in the output characteristics, the current due to the impact ionization in the drift region (I KIRK ) needs to be accurately modeled. An external current controlled current source (CCCS) is included in the proposed subcircuit model to model I KIRK accurately. The model is validated for a set of channel and drift lengths to demonstrate the scalability of the model. The accuracy of the proposed subcircuit model is verified using 2-D numerical simulations.

A New LDMOSFET with Tunneling Junction for Improved On-State Performance

We propose a new laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) with a tunneling junction at the drain side to reduce its on-state resistance and improve the peak transconductance significantly, as compared with the conventional LDMOSFET device. Using 2-D numerical simulations in an ATLAS device simulator, we have shown that the proposed tunneling junction at the drain side results in 25% reduction in RON and 20% improvement in peak transconductance in an ~ 40-V device without any significant degradation in other performance parameters.

Drain efficiency amplifier of 50% with optimized power range for CDMA base station

AbstractA novel high‐efficiency Doherty amplifier is presented here.A carrier amplifier and a peak amplifier are set to asymmetrical drain voltages to extend the power range where a high efficiency of the amplifier is maintained. In Doherty amplifier, matching circuits of the carrier amplifier and peak amplifier are designed for each drain voltage so that the efficiency and signal linearity of the amplifier at a 7.2 dB back‐off point from its saturated output power become higher than those of a conventional amplifier. A Doherty amplifier containing laterally‐diffused metal‐oxide semiconductor field‐effect transistors achieves an adjacent channel leakage power ratio of −30.89 dBc and a drain efficiency of 50% at an output power of 49.3 dBm. This is the highest drain efficiency of a Doherty amplifier for a CDMA signal to the best of the authors' knowledge. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1244–1246, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25195

A high‐frequency and high‐power quasi‐class‐E amplifier design using a finite bias feed inductor

AbstractThis paper presents a design method for a compact high‐efficiency quasi‐class‐E amplifier, using a finite bias feed inductor. It is very difficult to achieve proper class‐E operation from high‐power transistors operating in the high‐frequency region because of their internal parasitic components. To mitigate the effects of internal parasitic components on class‐E operation, a finite DC feed inductance is introduced to resonate out the capacitive parasitic components. A quasi‐class‐E amplifier with a finite DC feed inductor was designed and implemented at 1.2 GHz using a high‐power laterally diffused metal‐oxide‐semiconductor field‐effect transistor (LDMOSFET). We compared simulated time domain current and voltage waveforms with ideal ones. As the test results indicated, power‐added efficiency as high as 70.4% was achieved, at high output power of 39.55 dBm, without losing the circuits' simplicity, one of the most important advantages of class‐E operation. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1114–1118, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI.10.1002/mop.22368