Lateral Transistor Research Articles

Dependence on Base Width and Doping Concentration of Current Degradation in Gate-controlled Lateral PNP Bipolar Transistors Exposed to Reactor Neutrons and Gamma Rays

Bipolar devices are widely used in the nuclear reactor control system, and the radiation effects on them are very important to reactor operation. The lateral PNP bipolar transistor is a radiation-sensitive structure in bipolar integrated devices. Its degradation under irradiation is the primary cause for functional failures of bipolar integrated devices. It is useful to understand the radiation response of the transistors to find better design strategies for radiation hardness. Three kinds of gate-controlled lateral PNP bipolar transistors (GCLPNPs) with different base widths and doping concentrations are specially designed to explore base current degradation induced by reactor neutrons and gamma rays. Dependence on base width and doping concentration of the degradation is analyzed in this work and the results are beneficial to radiation-hardening design of the lateral PNP bipolar transistor.

Slanted Tri-Gates for High-Voltage GaN Power Devices

In this letter, we introduce and demonstrate the concept of slanted tri-gates to enhance the breakdown voltage ( ${V}_{{\text {BR}}}$ ) in lateral GaN power devices. Conventionally, field plates (FPs) are used to enhance the ${V}_{{\text {BR}}}$ by distributing more homogeneously the electric field near the gate electrode, which is mainly determined by their pinch-off voltage ( ${V}_{\text {p}}$ ). These FPs however rely on a vertical approach, in which ${V}_{\text {p}}$ is usually designed via the thickness of the FP oxide. On the other hand, the slanted tri-gate relies on a lateral design to tailor its ${V}_{\text {p}}$ , by simply changing the width ( ${w}$ ) of their nanowires lithographically. Here, we demonstrate this concept for AlGaN/GaN-on-silicon MOSHEMTs resulting in an increase of ~500 V in ${V}_{{\text {BR}}}$ compared with the counterpart planar devices. These devices presented a high ${V}_{{\text {BR}}}$ of 1350 V with a small gate-to-drain separation ( ${L}_{{\text {GD}}}$ ) of $10~\mu \text{m}$ , along with a record high-power figure-of-merit of 1.2 GW/cm $^{{2}}$ among GaN-on-silicon lateral transistors.

A Snapback-Free Fast-Switching SOI LIGBT With Polysilicon Regulative Resistance and Trench Cathode

A snapback-free fast-switching lateral insulated-gate bipolar transistor (LIGBT) with low power loss and high ruggedness is proposed and investigated by simulation. The proposed device features a polysilicon regulative resistance (PR) and a trench cathode (TC), named PRTC LIGBT. The PR is employed to not only suppress the snapback effect by regulating the voltage drop between P+ anode and N-buffer, but also improve the tradeoff between the on-state voltage drop ( $\text{V}_{ \mathrm{\scriptscriptstyle ON}})$ and turn-off loss ( $\text{E}_{ \mathrm{\scriptscriptstyle OFF}})$ . The TC widens the hole current path and decreases the distributed resistance under N+ cathode, and thus delivers a high latch-up ruggedness. Additionally, the PRTC LIGBT exhibits a blocking characteristic irrelevant to P+ anode concentration (NA), like a p-i-n diode (P-well, N-drift, and N-buffer), owing to its undepleted N-buffer region. Simulation results show that the PRTC LIGBT eliminates the snapback and reduces the $\text{E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 28% compared to the segmented trenches in the anode (STA) region LIGBT. Its short-circuit time is prolonged by 53% and 40% compared to those of the STA LIGBT and PR LIGBT (without TC), respectively.

Evaluation of a “Field Cage” for Electric Field Control in GaN-Based HEMTs That Extends the Scalability of Breakdown Into the kV Regime

A distributed impedance “field cage” structure is proposed and evaluated for electric field control in GaN-based, lateral high electron mobility transistors operating as kilovolt-range power devices. In this structure, a resistive voltage divider is used to control the electric field throughout the active region. The structure complements earlier proposals utilizing floating field plates that did not employ resistively connected elements. Transient results, not previously reported for field plate schemes using either floating or resistively connected field plates, are presented for ramps of $dV_{\mathrm {ds}}/dt = 100$ V/ns. For both dc and transient results, the voltage between the gate and drain is laterally distributed, ensuring that the electric field profile between the gate and drain remains below the critical breakdown field as the source-to-drain voltage is increased. Our scheme indicates promise for achieving the breakdown voltage scalability to a few kilovolts.

(Keynote) Advances in Ga2O3 Processing and Devices

Ga2O3 is a promising wide bandgap semiconductor for applications including power electronics and photodetectors and is available in large diameter, high quality bulk crystalline form. There have been many recent advances on both the materials and processing/device fronts and in this chapter we discuss some developments in Ohmic contacts, plasma etching, understanding of the role of hydrogen and high breakdown rectifier structures. Ga2O3 appears to have a role in expanding applications for high-speed or high-power semiconductor electronic devices. The high-power/high-voltage market is currently primarily served by Si and SiC devices. Ga2O3 is the leading candidate to address the ultra-high power market (>1kW). We will discuss recent progress in developing Ohmic contacts using interlayers of ITO or AZO, high density plasma etching using ICP discharges and the resultant etch rates, morphologies and near-surface damage, behavior of hydrogen incorporated during ion implantation or plasma exposure, measurement of band offsets with dielectrics and application of these processes to vertical and lateral transistor structures.

Hot-Carrier-Induced Degradations and Optimizations for Lateral DMOS Transistor With Multiple Floating Poly-Gate Field Plates

The electrical parameters degradations of lateral double-diffused MOS with multiple floating poly-gate field plates under different stress conditions have been investigated experimentally. For the maximum substrate current ( ${I}_{{\text {submax}}})$ stress, the increased interface states at the bird’s beak mainly result in an on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}})$ increase at the beginning of the stress, while hot holes injection and trapping into the oxide beneath the edge of real poly-gate turns out to be the dominating degradation mechanism after around 800-s stress, making the ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ decrease. For the maximum operating gate voltage ( ${V}_{{\text {gmax}}})$ stress, the trapped hot electrons in the channel region bring an increase in threshold voltage ( ${V}_{{\text {th}}})$ and ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ , while the generation of large numbers of interface states at the bird’s beak further dramatically increases the ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ . A novel device structurewith a poly-gate partly recessed into the field oxide has been presented to decrease the hot-carrier-induced degradations.

Lossless turn-off switching projection of lateral and vertical GaN power field-effect transistors

New physical insights into switching loss evaluation are applied to GaN power field-effect transistors, including p-AlGaN gate HEMTs, MOS channel HEMTs, and vertical UMOSFETs. Internal channel current is used to calculate true switching loss values for both turn-on and -off. In contrast to conventional terminal current-based loss calculations, energy stored in device output capacitances during turn-off and dissipated during turn-on is counted as turn-on loss rather than turn-off loss. At appropriate RG and off-state VG values, lossless turn-off can be achieved for MOS channel HEMTs and UMOSFETs, but not for p-AlGaN gate HEMTs. In appropriate circuit applications, near zero total switching loss can be realized by combining lossless turn-off and zero-voltage turn-on.

Band-to-band tunneling in Γ valley for Ge source lateral tunnel field effect transistor: Thickness scaling

The direct and indirect valleys in Germanium (Ge) are separated by a very small offset, which opens up the prospect of direct tunneling in the Γ valley of an extended Ge source tunnel field effect transistor (TFET). We explore the impact of thickness scaling of extended Ge source lateral TFET on the band to band tunneling (BTBT) current. The Ge source is extended inside the gate by 2 nm to confine the tunneling in Ge only. We observe that as the thickness is scaled, the band alignment at the Si/Ge heterojunction changes significantly, which results in an increase in Ge to Si BTBT current. Based on density functional calculations, we first obtain the band structure parameters (bandgap, effective masses, etc.) for the Ge and Si slabs of varying thickness, and these are then used to obtain the thickness dependent Kane's BTBT tunneling parameters. We find that electrostatics improves as the thickness is reduced in the ultra-thin Ge film (≤10 nm). The ON current degrades as we scale down in thickness; however, the subthreshold slope (SSAVG) improves remarkably with thickness scaling due to subsurface BTBT. We predict that 8 nm thin devices offer the best option for optimized ON current and SSAVG.

The Effect of Interfacial Charge on the Development of Wafer Bonded Silicon-on-Silicon-Carbide Power Devices

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer.

Cyclical Thinning of Black Phosphorus with High Spatial Resolution for Heterostructure Devices.

A high spatial resolution, cyclical thinning method for realizing black phosphorus (BP) heterostructures is reported. This process utilizes a cyclic technique involving BP surface oxidation and vacuum annealing to create BP flakes as thin as 1.6 nm. The process also utilizes a spatially patternable mask created by evaporating Al that oxidizes to form Al2O3, which stabilizes the unetched BP regions and enables the formation of lateral heterostructures with spatial resolution as small as 150 nm. This thinning/patterning technique has also been used to create the first-ever lateral heterostructure BP metal oxide semiconductor field-effect transistor (MOSFET), in which half of a BP flake was thinned in order to increase its band gap. This heterostructure MOSFET showed an ON/OFF current ratio improvement of 1000× compared to homojunction MOSFETs.

The high temperature DC characteristics of a high voltage lateral insulated-gate bipolar transistors with NPN anode in junction isolation technology

The high temperature DC characteristics of a high-voltage bulk Si lateral insulated-gate bipolar transistor in junction isolation (JI-LIGBT) technology is studied intensively in this paper. The current density distribution in the off-state at different temperatures of three types of device structure is compared. By using the Quasi-vertical DMOSFET (QVDMOS or multi-channel, MC) structure, the electron injection from the channel into the n-drift region is significantly enhanced, and the current density is improved. In addition, by extending the p-top layer to the NPN anode not only improves the breakdown voltage but also reduces the substrate current as well as ensures high temperature stability.

Calibrated Nanoscale Dopant Profiling and Capacitance of a High-Voltage Lateral MOS Transistor at 20 GHz Using Scanning Microwave Microscopy

We quantitatively image the doping concentration and the capacitance of a high-voltage lateral metal-oxide-semiconductor transistor device with a channel length of 0.5 μm at 20-GHz frequency using scanning microwave microscopy (SMM). The transistor is embedded in a deep n-well forming a flat pn-junction with the p-substrate, with the shape of the pn-junction resolved in the SMM images. Calibrated dC/dV imaging of the device revealed doping concentration values in the range of 1015–1019 atoms/cm 3, including the p-body, n-drift region, n-source-diffusion, as well as all the pn-junctions and the silicon/oxide interfaces at a minimum feature size of 350 nm and SMM electrical resolution of 60 nm. SMM doping concentrations have been compared with technology computer-aided design simulations, resulting in a quantitative agreement between model and experiment. dC/dV images have been acquired at different tip dc bias voltages, allowing to determine the p and n dopant polarity. From the reflection scattering S11 signal calibrated capacitance measurements have been obtained from the various transistor regions in the range of 300 aF to 1 fF. The results suggest that both dC/dV dopant profiling and capacitance measurements can be used for quantitative nanoscale semiconductor device imaging.

Fringe field control of one-dimensional room temperature sub-band resolved quantum transport in site controlled AlGaN/GaN lateral nanowires (Phys. Status Solidi A 2∕2017)

GaN quantum nanowire based devices are predicted to provide a host of benefits owing to two-dimensional confinement. However, the regular patterned formation of nanowires which actually show quantum confined effects has remained a daunting challenge for GaN. Here, Kumar et al. (article No. 1600620) demonstrate that an array of regular patterned lateral nanowires of aspect ratio > 103 or higher with width <5 nm can be formed by a combination of dry and crystallographic anisotropic wet-etching processes. The large inter-subband separation leads to room-temperature sub-band resolved quantum transport in these devices as an evidence of the strong two-dimensional confinement. The drain to source current of the nanowire is controlled by the fringe field arising out of a non-contacting gate. This scheme shows an alternative method to control gate field without the problem of sidewall leakage. The main figure of the cover image shows an SEM of the fringe field lateral nanowire transistor. A typical cross-section of the nanowire is shown in the lower panel. The upper panel shows the quantum capacitance for a hypothetical 2-D and 1-D nanowire systems highlighting the importance of quantum confinement in these systems.

Impact of doping and diameter on the electrical properties of GaSb nanowires

The effect of doping and diameter on the electrical properties of vapor-liquid-solid grown GaSb nanowires was characterized using long channel back-gated lateral transistors and top-gated devices. The measurements showed that increasing the doping concentration significantly increases the conductivity while reducing the control over the channel potential and shifting the threshold voltage, as expected. The highest average mobility was 85 cm2/V·s measured for an unintentionally doped GaSb nanowire with a diameter of 45 nm, whereas medium doped nanowires with large diameters (81 nm) showed a value of 153 cm2/V·s. The mobility is found to be independent of nanowire diameter in the range of 36 nm–68 nm, while the resistivity is strongly reduced with increasing diameter attributed to the surface depletion of charge carriers. The data are in good agreement with an analytical calculation of the depletion depth. A high transconductance was achieved by scaling down the channel length to 200 nm, reaching a maximum value of 80 μS/μm for a top-gated GaSb nanowires transistor with an ON-resistance of 26 kΩ corresponding to 3.9 Ω.mm. The lowest contact resistance obtained was 0.35 Ω·mm for transistors with the highest doping concentration.

On Razors Edge: Influence of the Source Insulator Edge on the Charge Transport of Vertical Organic Field Effect Transistors

ABSTRACTTo benefit from the many advantages of organic semiconductors like flexibility, transparency, and small thickness, electronic devices should be entirely made from organic materials. This means, additionally to organic LEDs, organic solar cells, and organic sensors, we need organic transistors to amplify, process, and control signals and electrical power. The standard lateral organic field effect transistor (OFET) does not offer the necessary performance for many of these applications. One promising candidate for solving this problem is the vertical organic field effect transistor (VOFET). In addition to the altered structure of the electrodes, the VOFET has one additional part compared to the OFET – the source-insulator. However, the influence of the used material, the size, and geometry of this insulator on the behavior of the transistor has not yet been examined. We investigate key-parameters of the VOFET with different source insulator materials and geometries. We also present transmission electron microscopy (TEM) images of the edge area. Additionally, we investigate the charge transport in such devices using drift-diffusion simulations and the concept of a vertical organic light emitting transistor (VOLET). The VOLET is a VOFET with an embedded OLED. It allows the tracking of the local current density by measuring the light intensity distribution.We show that the insulator material and thickness only have a small influence on the performance, while there is a strong impact by the insulator geometry – mainly the overlap of the insulator into the channel. By tuning this overlap, on/off-ratios of 9x105 without contact doping are possible.

Molecular beam epitaxy growth of atomically ultrathin MoTe2 lateral heterophase homojunctions on graphene substrates

Van der Waals epitaxy growth of two-dimensional materials promise controllable fabrication of novel artificial heterostructures. Here, we report molecular beam epitaxy growth of continuous molybdenum ditelluride (MoTe2) films on graphene substrates with good stoichiometry in both 2H and 1T′ phases. Post-growth annealing reveal phase transition suppressed in Te-rich atmosphere, through in-situ scanning tunneling microscopy/spectroscopy and X-ray photoelectron spectroscopy. Our results suggest a new route to fabricate atomically ultrathin MoTe2 lateral heterophase homojunctions, showing potential applications in future lateral thin-film transistors.

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to silicon carbide (SiC). This novel silicon-on-silicon-carbide (Si/SiC) substrate solution promises to combine the benefits of silicon-on-insulator (SOI) technology (i.e device confinement, radiation tolerance, high and low temperature performance) with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance). Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

Graphene as an electrode for solution-processed electron-transporting organic transistors.

Organic field-effect transistors (OFETs) are fundamental building blocks for plastic electronics such as organic photovoltaics or bendable displays with organic light emitting diodes, and radio-frequency identification (RFID) tags. A key part in the performance of OFET is the organic material constituting the channel. OFETs based on solution-processed polymers represent a new class of organic electronic devices. Recent developments in upscale solution-processed polymers have advanced towards high throughput, low-cost, and environmentally friendly materials for high-performance applications. Together with the integration of high performance materials, another enduring challenge in OFET development is the improvement and control of the injection of charge carriers. Graphene, a two-dimensional layer of covalently bonded carbon atoms, is steadily making progress into applications relying on van der Waals heterointerfaces with organic semiconductors. Here, we demonstrate the versatile operation of solution-processed organic transistors both in lateral and vertical geometries by exploiting the weak-screening effect and work function modulation properties of graphene electrodes. Our results demonstrate a general strategy for overcoming traditional noble metal electrodes and to integrate graphene with solution-processed Polyera ActiveInk™ N2200 polymer transistors for high-performance devices suitable for future plastic electronics.

Limitations on Lateral Nanowire Scaling Beyond 7-nm Node

In this letter, we have studied the impact on lateral nanowire transistor’s (LNW) performance of reducing the wire diameter from 7 nm to 5 nm. As technology scaling continues, the LNW device size is scaled here for beyond 7-nm nodes. Reducing the NW’s gate length causes huge degradation in electrostatic control of the device. The degraded electrostatic is improved by reducing the wire diameter. DC and ring oscillator benchmark have been performed for different NW size for sub-7-nm node using TCAD-based compact models. Using the 5-nm-diameter-based LNW at the gate length of 10 nm around 8-mV/decade subthreshold slope improvement is observed as compared with the 7-nm-diameter LNW. This leads to the possibility of improved performances for the 5-nm-diameter-based device. The NW device, with 5-nm wire diameter and 10-nm gate length can provide some area gain. Although the 5-nm-diameter device increases channel confinement, due to the reduced drive current and increased parasitics, overall device speed is lagging behind the 7-nm diameter device.

Two-zone SiGe base heterojunction bipolar charge plasma transistor for next generation analog and RF applications

For next generation terahertz applications, heterojunction bipolar transistor (HBT) with reduced dimensions and charge plasma (CP) can be a potential candidate due to simplified and inexpensive process. In this paper, a symmetric lateral two-zone SiGe base heterojunction bipolar charge plasma transistor (HBCPT) with an extruded (extended) base is proposed and its performance at circuit level is studied. The linearly graded electric field in the proposed HBCPT provides improved self gain (β) and cut-off frequency (fT). Two-dimensional (2-D) TCAD and small-signal model based simulations of the proposed HBCPT demonstrates high self gain β 35–172.93 and fT of 1–4 THz for different device parameters. Moreover, fT of 1104.9 GHz and β of 35 can be achieved by decreasing Nb up to 8.2×1017cm−3. Although, fT of 2 THz and 4 THz can also be achieved by reducing the base resistance up to 10 Ω and increasing the emitter/collector length up to 63 nm, respectively. The small-signal analysis of common-emitter amplifier based on the proposed HBCPT demonstrate high voltage gain of 50.11 as compared to conventional HBT (18.1).