Lateral Transistor Research Articles

A nonvolatile magnon field effect transistor at room temperature

Information industry is one of the major drivers of the world economy. Its rapid growth, however, leads to severe heat problem which strongly hinders further development. This calls for a non-charge-based technology. Magnon, capable of transmitting spin information without electron movement, holds tremendous potential in post-Moore era. Given the cornerstone role of the field effect transistor in modern electronics, creating its magnonic equivalent is highly desired but remains a challenge. Here, we demonstrate a nonvolatile three-terminal lateral magnon field effect transistor operating at room temperature. The device consists of a ferrimagnetic insulator (Y3Fe5O12) deposited on a ferroelectric material [Pb(Mg1/3Nb2/3)0.7Ti0.3O3 or Pb(Zr0.52Ti0.48)O3], with three Pt stripes patterned on Y3Fe5O12 as the injector, gate, and detector, respectively. The magnon transport in Y3Fe5O12 can be regulated by the gate voltage pulses in a nonvolatile manner with a high on/off ratio. Our findings provide a solid foundation for designing energy-efficient magnon-based devices.

A Novel Isolation Approach for GaN-Based Power Integrated Devices.

This paper introduces a novel technology for the monolithic integration of GaN-based vertical and lateral devices. This approach is groundbreaking as it facilitates the drive of high-power GaN vertical switching devices through lateral GaN HEMTs with minimal losses and enhanced stability. A significant challenge in this technology is ensuring electrical isolation between the two types of devices. We propose a new isolation method designed to prevent any degradation of the lateral transistor's performance. Specifically, high voltage applied to the drain of the vertical GaN power FinFET can adversely affect the lateral GaN HEMT's performance, leading to a shift in the threshold voltage and potentially compromising device stability and driver performance. To address this issue, we introduce a highly doped n+ GaN layer positioned between the epitaxial layers of the two devices. This approach is validated using the TCAD-Sentaurus simulator, demonstrating that the n+ GaN layer effectively blocks the vertical electric field and prevents any depletion or enhancement of the 2D electron gas (2DEG) in the lateral GaN HEMT. To our knowledge, this represents the first publication of such an innovative isolation strategy between vertical and lateral GaN devices.

(Electronics and Photonics Division Award) Research Advances Wide- and Ultrawide-Bandgap Power Switching Devices

Wide bandgap semiconductors such as SiC and GaN (WBG) and emerging ultrawide-bandgap materials such as Ga2O3, AlGaN, and Diamond (UWBG) represent the next-generation materials for high performance medium voltage and high voltage power switch technology. Such devices have a wide range of immediate Naval applications, including high-power satellite communications and radar, unmanned underwater and aerial vehicles, ship drive components, and hybrid vehicle inverters. Vertical SiC power device technology has matured rapidly over the past two decades, owing to advances in substrates, a fundamental understanding of epitaxial growth to eliminate performance-limiting defects, as well as device design breakthroughs. This has enabled breakthroughs in highly integrated module design for medium voltage power conversion with switching frequency >100 kHz. In parallel, lateral GaN-based high electron mobility transistor (HEMT) technology has been highly successful for RF power amplifiers and is well positioned to supersede GaAs-based microwave circuits. Recently, GaN-based vertical and lateral power devices have attracted significant interest due to promising device results coupled with progress in native substrate, epitaxial growth, and processing technology developments. This seminar will present an overview of the WBG/UWBG power device efforts at NRL. This research has four primary focus areas – 1) thermal management in III-N power device structures by diamond thin film integration, 2) characterization of substrate materials and homoepitaxial layers used for drift regions of power devices identify appropriate specifications and benchmark performance, 3) process module development, particularly for selective area doping by ion implantation, and 4) pilot production manufacturing of 1.2kV-class PiN diodes including reliability assessments to identify and mitigate performance limiting defects.

(Invited) Organic Permeable-Base Transistors: Physically Motivated Simplification of Device Structure for Modeling and Simulation

Vertical organic transistors are an attractive alternative to conventional lateral organic transistors due to their high DC and AC performance [1]. Among them, organic permeable-base transistors (OPBTs) are considered to be promising candidates for low-voltage flexible electronics due to their unique properties. However, their complex structures necessitate a deeper understanding of their operational mechanisms and the underlying physics [2, 3]. Compact models are essential for designing and optimizing integrated circuits (ICs). They are also used to develop and improve new transistor technologies. Analytical modeling of OPBTs based on geometrical parameterization has been reported [4]. A Gaussian DOS charge-based model has also been developed for organic transistors and adapted to OPBTs [5]. Their AC performance have been analyzed quantitatively, paving the way to reach GHz high frequency in organic transistors [6].In this work, we report on the simplification of the complex structure of OPBTs in terms of their DC performance and characteristics. This simplification makes it easier to simulate, analyze, understand, and explain the working principle, optimize, and model OPBTs. We calibrate the TCAD simulation to the fabricated device structure and its characteristics to ensure that the simulation represents the OPBT to validate this simplification. Based on the calibrated TCAD simulation, we demonstrate that the characteristics of fabricated OPBTs with n pinholes (number of pinholes is determined by the density of pinholes) are equivalent to those of n single pinhole OPBTs connected in parallel. This is proved by physical models and arises from the fact that the pinholes are shielded by the base electrode, resulting in no electrostatic interaction known as screening effects between them. Therefore, it appears as multiple pinholes (transistors) have been fabricated in a single device (OPBT). Thus, one needs to analyze, optimize, and model a single pinhole (where the pinhole density determines the performance and specific structural dimension of the single pinhole) from the fabricated OPBTs and multiply its DC characteristics by the number of pinholes. The new simplification and formulation show good agreement with the experimental data of fabricated OPBTs, as well as the results obtained from TCAD simulations and a Gaussian DOS charge-based model. Acknowledgements: This project is funded by the German Research Foundation (DFG) under the grants "DA 2578/2-1" and "KL 2961/10-1", the Spanish Ministry of Science (PRX21/00726), and the EU EIC-PATHFINDER (BAYFLEX, no 101099555).

A fast-switching and ultra low-loss snapback-free reverse-conducting SOI-LIGBT with Adjustable Carrier Technology

A snapback-free Reverse-Conduction Silicon On Insulator Lateral Insulate Gate Bipolar Transistor (RC SOI-LIGBT) with Adjustable Carrier Technology (ACT LIGBT) is proposed in this paper. ACT LIGBT adds Semi-Insulating Polycrystalline Silicon (SIPOS) material on the extended gate dielectric, and introduces the potential of the surface SIPOS into the P-type drift region (P-Drift) through SiO2 trenches. ACT LIGBT generates the inversion layer of electrons in the P-Drift due to the linear potential distribution brought by the high resistance characteristic of SIPOS, resulting in the adjustment of the number of electrons and holes, and forming the technology of ACT. Additionally, ACT LIGBT adds a hole extraction path during it turned off. Meanwhile, compared to SSA LIGBT, ACT LIGBT optimized the BV (700V) by 34 %, while also optimizing the Von (1.69V) by 25 %, turn-off time (toff = 12ns) by 92 %, turn-off loss (Eoff = 0.69 mJ/cm2) by 79 %, and reverse recovery charge (Qrr = 32.98 μC/cm2) by 32.5 %, ultimately achieving a better compromise relationship among BV, Von, toff, Eoff, and Qrr.

Demonstration of a lateral p-NiO/n-GaN JFET fabricated by selective-area regrowth

In this paper, we demonstrated experimentally a lateral GaN-based junction field effect transistor (JFET). A selective area regrowth of p-NiO on the as-grown n-GaN channel layer was developed by magnetron sputtering at room temperature to form the p–n junction. A self-aligned gate process and a post metal annealing process were employed to improve the device performances. The measured results show that the annealed JFET exhibits an ON/OFF ratio exceeding 106 and a higher breakdown voltage up to 814 V without any terminal structure. The breakdown voltage is determined by the reverse breakdown of parasitic PN junction between gate and drain. Further, the threshold voltage of the p-NiO/n-GaN JFET exhibits excellent temperature stability in the range of 300–500 K.

High-density vertical sidewall MoS2 transistors through T-shape vertical lamination

Vertical transistors, in which the source and drain are aligned vertically and the current flow is normal to the wafer surface, have attracted considerable attention recently. However, the realization of high-density vertical transistors is challenging, and could be largely attributed to the incompatibility between vertical structures and conventional lateral fabrication processes. Here we report a T-shape lamination approach for realizing high-density vertical sidewall transistors, where lateral transistors could be pre-fabricated on planar substrates first and then laminated onto vertical substrates using T-shape stamps, hence overcoming the incompatibility between planar processes and vertical structures. Based on this technique, we vertically stacked 60 MoS2 transistors within a small vertical footprint, corresponding to a device density over 108 cm−2. Furthermore, we demonstrate two approaches for scalable fabrication of vertical sidewall transistor arrays, including simultaneous lamination onto multiple vertical substrates, as well as on the same vertical substrate using multi-cycle layer-by-layer laminations.

Enhancement-mode Ga2O3 FETs with an unintentionally doped (001) β-Ga2O3 channel layer grown by metal-organic chemical vapor deposition

High-quality unintentionally doped (UID) (001) β-Ga2O3 homoepitaxial films were grown on native substrates through metalorganic CVD. The surface parallel grooves were repaired under low temperature and pressure conditions, reaching the surface roughness of 2.22 nm and the high electron mobility of 74.6 cm2/Vs. Enhancement-mode MOSFETs were fabricated on the UID β-Ga2O3 film, showing a positive turn-on threshold gate voltage of 4.2 V and a breakdown voltage of 673 V. These results can serve as a reference for (001)-oriented lateral Ga2O3 power transistors and may contribute to the development of Ga2O3 power devices.

CVD graphene contacts for lateral heterostructure MoS2 field effect transistors

Intensive research has been carried out on two-dimensional materials, in particular molybdenum disulfide, towards high-performance field effect transistors for integrated circuits1. Fabricating transistors with ohmic contacts is a challenging task due to the formation of a high Schottky barrier that severely limits the performance of the transistors for real-world applications. Graphene-based heterostructures can be used in addition to, or as a substitute for unsuitable metals. In this paper, we present lateral heterostructure transistors made of scalable chemical vapor-deposited molybdenum disulfide and chemical vapor-deposited graphene achieving a low contact resistances of about 9 kΩ·µm and high on/off current ratios of 108. Furthermore, we also present a theoretical model calibrated on our experiments showing further potential for scaling transistors and contact areas into the few nanometers range and the possibility of a substantial performance enhancement by means of layer optimizations that would make transistors promising for use in future logic integrated circuits.

Lateral ionic-gated graphene synaptic transistor with transition from paired-pulse facilitation to depression for filtering and image recognition

The transition from paired-pulse facilitation to paired-pulse depression is of significant importance for regulating biologic neural network. Here, we fabricate and investigate a lateral ionic-gated graphene synaptic transistor (GST) with short gate length. We control the channel current via e-field-dependent movement and diffusion of ions for realizing the transition from paired-pulse facilitation to depression. This phenomenon comes from the over-diffusion and trapping of a finite number of ions and the short ion-diffusion length under large negative gate pulse stimuli. This device successfully emulates facilitation and depression synaptic functions, for leveraging the accumulation, migration and diffusion of ions. Moreover, enhanced high-pass filtering and conversion from long-term depression to long-term potentiation are achieved by changing pulses time interval. Our results indicate that our device possesses excellent frequency-dependent synaptic plasticity, making it highly suitable for information filtering up to 33 Hz in neuromorphic systems, and image edge enhancement for neural image processing. In additional, a simulated artificial neural network built on lateral ionic-gated GSTs for handwritten digit recognition can achieve a learning accuracy of 82.4 %.

Reduced temperature in lateral (AlxGa1−x)2O3/Ga2O3 heterojunction field effect transistor capped with nanocrystalline diamond

The low thermal conductivity of β-Ga2O3 is a significant concern for maximizing the potential of this ultra-wide bandgap semiconductor as a power switching device technology. Here, we report on the use of nanocrystalline diamond (NCD) deposited via microwave plasma enhanced chemical vapor deposition (MP-CVD) as a top-side, device-level thermal management solution on a lateral β-Ga2O3 transistor. NCD was grown via MP-CVD on β-(AlxGa1−x)2O3/β-Ga2O3 heterostructures prior to the gate formation of the field-effect transistor. A reduced growth temperature of 400 °C and a SiNx barrier layer were used to protect the oxide semiconductors from etching in the MP-CVD H2 plasma environment. Raman spectroscopy showed a highly sp3-bonded NCD film was obtained at 400 °C, with grain size of about 50–100 nm imaged via atomic force microscopy. The incorporation of the NCD heat-spreading layer resulted in a β-(AlxGa1−x)2O3/β-Ga2O3 heterostructure field-effect transistor showing a decrease in the total thermal resistance at the gate by 42%. The fabrication process, including the NCD etch in the gate region, will need to be improved to minimize the impact of these processes on important device characteristics (i.e., drain current, threshold voltage, and leakage current).

Accumulation and removal of Si impurities on β-Ga2O3 arising from ambient air exposure

Here, we report that a source of Si impurities commonly observed on (010) β-Ga2O3 is from exposure of the surface to air. Moreover, we find that a 15 min hydrofluoric acid (HF) (49%) treatment reduces the Si density by approximately 1 order of magnitude on (010) β-Ga2O3 surfaces. This reduction in Si is critical for the elimination of the often observed parasitic conducting channel, which negatively affects transport properties and lateral transistor performance. After the HF treatment, the sample must be immediately put under vacuum, for the Si fully returns within 10 min of additional air exposure. Finally, we demonstrate that performing a 30 min HF (49%) treatment on the substrate before growth has no deleterious effect on the structure or on the epitaxy surface after subsequent Ga2O3 growth.

Calculation of GaInSb PNP lateral HBT for complementary bipolar logic technology

In this study, the power consumption and speed of a GaInSb PNP lateral heterojunction bipolar transistor were estimated for applications in complementary bipolar logic circuits. At the supply voltage of 250 mV, the current gain is over 1000, on/off power consumption ratio is approximately 180, and delay time is 2.6 ps. However, the characteristics degrade rapidly at voltages greater than 300 mV, owing to deep saturation and high-level injection.

Sensitivity Analysis of a Double Source Stack Lateral TFET-Based Gas Sensor

Metal oxide semiconductor gas sensors are used recently in various roles and sectors for environmental safety as compared to other sensing technology due to its low cost, durability, longevity, and rapid sensing capability under humid condition. The current work proposes a dual stacked heterogeneous source lateral n type tunnel field-effect transistor (DSHS-nTFET) for gas sensing applications. The proposed device investigates the characteristics of the gas response. The stack source is designed to make it easier for electrons to tunnel through the tunnel barrier effectively so that the device sensitivity can be enhanced. In the device’s tunneling junction, the presence of the source stack boosts the electric field, reduces tunneling width, and then enhances the band-to-band tunneling. The gas density can be detected by modulating the work function of the metal gate present in the device. Catalytic metals used as gate contacts for this proposed double source stacking TFET design are explored for the purpose of detecting specific gases. Platinum (Pt), Cobalt (Co), Palladium (Pd), and Silver (Ag) are the metal gate electrodes utilised in this work to sense the target gases, like Carbon-mono Oxide (CO), Ammonia (NH3), Hydrogen (H2), and Oxygen (O2) respectively. The detection has been done by the electrodes work function variation due to the presence of gas density of the target gases. With the aid of the Sentaurus TCAD simulator, the suggested structure has been examined for a number of electrical parameters including electric field, surface potential, drain current, and numerous sensing characteristics pertaining to adsorption of gas molecules. According to the data achieved, the suggested DSHS-nTFET device displays a high Ion of 5.06 × 10−5 A/μ m, a low Ioff current of 3.76 × 10−20 A/μm, and also the Ion/Ioff ratio in the range of 1014. Furthermore, sensitivity parameters for DSHS-nTFET have also been examined and shown to be significantly improved. The sensitivity and reliability of the proposed sensor have also been investigated with respect to temperature fluctuations. It has been shown that the device is largely stable over the 200 K-400 K range.

Evaluation of custom-designed lateral power transistors in a silicon-on-insulator process in a synchronous buck converter

Most of todays power converters are based on power semiconductors, which are built in vertical power semiconductor processes. These devices result in limited packaging possibilities, which lead to physically long galvanic connections and therefore high external electromagnetic fields. These fields compromise power quality significantly. Therefore this paper examines the possibility to use lateral silicon-on-insulator power MOSFETs and uses the custom-made devices in a 48 V to 12 V synchronous buck converter in continuous conduction mode. The converter is designed based on custom made power transistors, implemented and verified by experimental results. The resulting efficiency of the 1 Wconverter is around 93 % across a wide load range and its temperature rise is less the 10 C. This leads to the conclusion, that modern lateral silicon-on-insulator power processes allow high integration of power stages and therefore promise lower emissions, leading to higher power quality.

Fully Electrically Modulated Hetero-Synapses With Lateral Multigate Ferroelectric Thin Film Transistor

Fully Electrically Modulated Hetero-Synapses With Lateral Multigate Ferroelectric Thin Film Transistor

Extraction of Sub-Threshold Mobility in Ga2O3 Lateral Transistors From AC Conductance

Extraction of Sub-Threshold Mobility in Ga₂O₃ Lateral Transistors From AC Conductance

Unipolar-Turn-Off Lateral Insulated-Gate Bipolar Transistor With On-Chip Biasing Circuit for Injection Control

Unipolar-Turn-Off Lateral Insulated-Gate Bipolar Transistor With On-Chip Biasing Circuit for Injection Control

(Best Paper Award, Invited) Manufacturing of Nanosheets and Multilayer Nanogaps in Silicon

Nanogap technology is the basic concept for many promising devices such as localized SOI, multichannel FETs, and resonant tunneling diodes.It will be shown that intrinsic bulk strain in single crystalline silicon can be used to create homogeneous nanogaps with a few nanometer gap distance. The strain has been created by epitaxial growth of Si1-xGex/Si multi-layer stacks on 200 mm (100) silicon wafers. The stacks were patterned by RIE to reveal the side walls for subsequent lateral etching with gaseous hydrochloric acid. In accordance with former investigations [1] we found that a selectivity up to 1000:1 for Si1-xGex/Si can be achieved for Ge-concentrations >30% and growth temperatures T<650°C. XRD measurements, SEM pictures and wagon wheel test structures prove that for the anisotropic lateral etching behavior intrinsic strain is the dominant factor. Furthermore, the crystal orientation plays a dominant role (Fig. 1). Based on this behavior multilayer nanogaps with spacings <10 nm had been fabricated.In a subsequent process nanogaps down to 5 nm have been successfully filled completely with dielectrics and/or metals by low temperature (T<450°C) plasma oxidation, LPCVD as well as ALD (Fig. 2). The resulting nanosheets can be used for device applications.Vertical diodes and lateral MOS transistors with nanogaps and nanosheets have been fabricated. Diodes with a SiO2 gap filling show perfect Fowler-Nordheim tunneling, which proves the high quality of the gap filling process. The electrical properties of nanogap-MOSFETs and various nanogap-diodes will be presented.[1] Destefanis et al., Semiconductor Sci. Technol. 23, 1 (2008) Fig. 1: Wagon wheel structure showing the etch anisotropy of 8 nm SiGe layer in Si Fig. 2: SEM cross section of a multistack of 6 SiGe layers selectively etched and completely filled with LPCVD oxide

Reliable p-type organic permeable base transistors—the missing component for integrated circuits

Due to their nm-range channel length, vertical organic transistors are gaining scientific interest to overcome the frequency limitations of lateral organic transistor. Especially, vertical organic permeable base transistors (OPBTs) with a structure resembling a vacuum-tube-triode stand out due to their excellent electrical performance. Recently, n-type OPBTs have been demonstrated with excellent performance and great potential to be applied in high-frequency logic circuits, display driving circuits, and light-emitting devices. However, achieving adequate p-type OPBTs to catch up with the performance of n-type devices is still challenging. Here, we report on the peculiar finding that the extended exposure of p-type OPBTs to ambient air during the fabrication has a positive effect on the electrical performance and tremendously improves the yield of devices to . Upon exposing the fresh device to air, oxygen diffuses into the semiconductor layer interacting with the base electrode, which facilitates the formation of pinholes in the base and creates an insulator layer around the base. Moreover, as oxygen acts as a p-dopants to the p-type semiconductors used in this work, the device performance is further improved, manifesting in an increased on-state current. However, as the exposure time increases, different p-type organic semiconductors show different behavior depending on their ionization potential. Comparing two semiconductor materials with a difference in their ionization potential of 0.4 eV, we show that long-term degradation could be effectively suppressed. Therefore, the positive effect of air exposure could be utilized to optimize p-type OPBTs, which offers a simple and universal way to construct high performance p-type OPBTs and possibly also complementary circuits.