Lateral PNP Transistors Research Articles

Exploration on Electrical Isolation Between High-Voltage SiC Thyristor and Small-Signal Devices for Smart Power Devices

The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Smart Discrete</i> concept which monolithically integrates a vertical high-voltage power device with low-voltage smart circuits has been widely adopted in silicon world for many years and may bring similar benefits to SiC world. For example, it is highly desirable to integrate a gate driver circuit onto a high-voltage SiC thyristor for ultra-fast turn-on. However, the electrical isolation between the vertical high-voltage power device and the low-voltage circuit elements remains a major technical challenge for silicon, and even more so for SiC due to the very limited processing options. In this article, we propose a combination of shallow junction isolation (JI) and partial dielectric isolation (DI) for high-voltage 4H-SiC smart thyristor, which is monolithically integrated with low-voltage nMESFET circuits. The characterization of fabricated devices and analysis of leakage currents across the isolation structure have been done to experimentally verify the feasibility of the isolation method. 8 V parasitic lateral NPNP thyristor between a 6.3 kV 4H-SiC thyristor and isolation moats, 175 V lateral PNP transistor between the passive resistor and isolation moats, and 10 V lateral reverse-biased p-n diode between nMESFET and isolation moats are experimentally demonstrated.

Novel dual-direction electrostatic discharge device with lateral PNP transistor

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge (ESD) as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are investigated. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in the DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than that of conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes the total triggering path of device shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than that of DDSCR. For thermal performance, most of the heat first accumulates near the lateral PNP transistor , and then the peak point of heat turns to main SCR path with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than that in DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Comparing with DDSCR, the conclusions are obtained. Under the condition of transmission line pulse (TLP) test simulation analyses, the triggering voltage is reduced by 31%, the holding voltage is increased by 16.8%, the ESD design window is optimized by 44.5%, and on-resistance is lower. When TLP stress is 2.67 A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed. When the VF-TLP stress is 0.1 A, the overshoot voltage of PNP_DDSCR device is the 37% of that of DDSCR device while the PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

Area-efficient dual-diode with optimized parasitic bipolar structure for rail-based ESD protections

Lateral parasitic PNP transistor inside P+/N-well diode is explored and investigated for the electrostatic discharge (ESD) protections in I/O interface integrated circuits (ICs). An analysis for the breakdown behavior of the lateral parasitic PNP transistor with base floating is presented for the first time. Simulations on the lateral parasitic PNP transistor have been performed to understand the effects of geometry parameters on current gain β, triggering voltage Vt1 and on-resistance RON. The test structures were fabricated using the UMC 65 nm low-k logic/mixed-mode CMOS process and characterized with the transmission line pulse (TLP) system. The TLP characterization results demonstrate that the triggering voltage Vt1 is strongly influenced by the base region (i.e., base width), and on-resistance RON is mainly affected by the collector region (i.e., collector width) for the finger-type parasitic PNP. Meanwhile, the scalability of thermal failure current It2 has been studied in terms of the periphery of the lateral parasitic PNP and the whole device width.

Quantitative study of the effect of gamma radiation on lateral PNP bipolar transistor

Bias-emission voltage and dose-dependent current gain is a key parameter in detecting the physical properties of the bipolar transistor. The first objective of this work is to measure the influences of gamma radiation on current gain in lateral PNP bipolar transistors. Substantial differences of the current gain as a function of voltage between bias and emission are observed. Then, based on the calculated results from the non-linear curve fitting method, the voltage between bias and emission-dependent current gain is theoretically explained successfully via the asymmetric peak function. The simulations agree very well with the observed curves (current gain versus voltage). The minimum correlation coefficient between the experimental and calculated data is 0.998. The average relative errors between the measured and modeled values do not exceed 9.14% in all considered cases. Finally, the mathematical relationships between the parameters, which serve to link the current gain and voltage together with dose, are obtained. Consequently, the current gain can be predicted by both voltage between bias and emission and dose using only one function. To the best knowledge of the author, the effects of gamma irradiation on the lateral PNP transistors are quantitatively discussed for the first time in current gain.

An LTspice Simulation Model of Gamma-radiation Effects and Annealing in a Voltage Regulator With a Lateral Serial PNP Transistor With Round Emitters

The aim of this paper was to determine the reasons for a complex radiation response of the commercial-off-the-shelf LM2940CT5 low-dropout voltage regulator. Examination of this circuit in a gamma-radiation environment disqualified its use when operated with relatively high output currents, while its radiation tolerance was satisfactory when load current was approximately one-tenth (or lower) of the nominal value. In order to obtain a more thorough insight into the radiation response of this integrated circuit, a detailed SPICE model was developed. This model enabled mutual comparison of the influence of serial and driver PNP power transistor parameters: forward emitter current gain, knee current and emitter resistance. The serial lateral PNP power transistor with round emitters was identified as the weakest element that crucially affected the entire circuit radiation tolerance. The effects of gamma-radiation were examined for total doses up to 500 Gy followed by three sequences of isothermal annealing. Detailed characteristics of Beta(Ic) were procured for four different kinds of bias and load conditions during irradiation. The emitter resistance increase of the serial power transistor was a primary reason for the low radiation tolerance of the entire voltage regulator; it was much more influential than the perceived decline of the PNP power transistor forward emitter current gain. The influence of bias and load conditions were analysed with buildup of interface traps and the oxide-trapped charge, which affected the radiation and post-irradiation response of the serial power transistor.

Effect of H2 on interface traps in the LPNP transistors caused by 3 MeV proton irradiations

In this paper, the effects of 3 MeV proton irradiations on gate controlled lateral PNP (GLPNP) transistors are investigated with and without molecular hydrogen (H2) soaking. The electrical parameters are measured in-situ during irradiation. Radiation defects indicated by 3 MeV protons are measured by deep level transient spectroscopy (DLTS). At a given the irradiation fluence, the degradation for the H2-soaked transistors is much larger than that for the non-soaked transistors. Excess base current (ΔIB) for the H2-soaked transistors is bigger than that for the non-soaked transistors at a given emitter-base voltage and the same irradiation fluence. According to the gate sweep (GS) curve, it can be calculated that the number of the interface traps of the H2-soaked transistors is significantly larger than that for the non-soaked transistors under the same fluence, as demonstrated by DLTS analyses. 3 MeV protons could mainly produce the ionization damage in the GLPNP transistors, displacement damage can be almost negligible. The results for the 70 keV electron irradiations further confirm that 3 MeV protons could mainly produce ionization damage in the GLPNP transistors and hydrogen can aggravate the formation of interface traps in GLPNP transistors.

Effect of protons located at different region in SiO2 layer on GLPNP transistors degradation

Based on 100-keV, 130-keV and 170-keV proton irradiations, the contribution of ionization damage to the electrical property degradation of gate controlled lateral PNP (GLPNP) transistors is investigated. The key electrical parameters are measured in-situ during irradiations. The radiation-induced defects are characterized by deep level transient spectroscopy (DLTS). Experimental results show that the same ionization dose of various energy protons caused different degradation of current gain in GLPNP transistors. The current gain of the irradiated transistors by 170-keV protons degrades obviously, while that of the irradiated transistors by 100-keV protons does not almost change. As the ionization dose increases, the excess base currents of the irradiated transistors by 170-keV and 130-keV protons increase. The ideality factor of the irradiated transistor by 170-keV protons changes, while that of the transistor irradiated by 130-keV protons does not change. The gate sweep (GS) curves show that the main ionization defects induced by different protons are the interface traps. Compared with the irradiated transistors by 100-keV and 130-keV protons, the irradiated transistors by 170-keV protons has a high gate sweep peak at the same dose indicating that the 170-keV protons induced more interface traps. Therefore, the protons located at different region in SiO2 of GLPNP transistors can induce different degree of degradation, and the location of the proton is closer to the Si/SiO2 interface, the number of the radiation-induced interface traps is the more.

Analysis of displacement damage effects on bipolar transistors irradiated by spallation neutrons

Displacement damage induced by neutron irradiation in China Spallation Neutron Source (CSNS) is studied on bipolar transistors with lateral PNP, substrate PNP, and vertical NPN configurations, respectively. Comparison of the effects on different type transistors is conducted based on displacement damage factor, and the differences are analyzed through minority carrier lifetime calculation and structure analysis. The influence of CSNS neutrons irradiation on the lateral PNP transistors is analyzed by the gate-controlled method, including the oxide charge accumulation, surface recombine velocity, and minority carrier lifetime. The results indicate that the total ionizing dose in CSNS neutron radiation environment is negligible in this study. The displacement damage factors based on 1-MeV equivalent neutron flux of different transistors are consistent between Xi’an pulse reactor (XAPR) and CSNS.

Hydrogen Soaking, Displacement Damage Effects, and Charge Yield in Gated Lateral Bipolar Junction Transistors

The effects of 70-keV and 1-MeV electron irradiations on gate-controlled lateral PNP (GLPNP) transistors are evaluated with and without molecular hydrogen (H2) soaking. At a given ionization dose, 1-MeV electron irradiation causes more degradation of current gain in GLPNP transistors that have not been soaked in H2 than 70-keV electrons. This is because linear bipolar transistors are sensitive to both ionization and displacement damage effects, and because 1-MeV electrons induce significant displacement damage in Si-based bipolar junction transistors and 70-keV electrons do not. In H2-soaked transistors, the degradation is much larger than in unsoaked devices, and similar amounts of degradation are observed for 70-keV electron irradiation and 1-MeV electron irradiation. This occurs because ionization–induced release, transport, and reactions of hydrogen in the bipolar-base oxide greatly enhance interface-trap buildup and dominate device response in H2-soaked devices, and because charge yield ratios for 70-keV and 1-MeV electron irradiations differ by less than ~20%.

Estimation of enhanced low dose rate sensitivity mechanisms using temperature switching irradiation on gate-controlled lateral PNP transistor**Project supported by the National Natural Science Foundation of China (Grant Nos. U1532261 and 1630141).

The mechanisms occurring when the switched temperature technique is applied, as an accelerated enhanced low dose rate sensitivity (ELDRS) test technique, are investigated in terms of a specially designed gate-controlled lateral PNP transistor (GLPNP) that used to extract the interface traps (Nit) and oxide trapped charges (Not). Electrical characteristics in GLPNP transistors induced by 60Co gamma irradiation are measured in situ as a function of total dose, showing that generation of Nit in the oxide is the primary cause of base current variations for the GLPNP. Based on the analysis of the variations of Nit and Not, with switching the temperature, the properties of accelerated protons release and suppressed protons loss play critical roles in determining the increased Nit formation leading to the base current degradation with dose accumulation. Simultaneously the hydrogen cracking mechanisms responsible for additional protons release are related to the neutralization of Not extending enhanced Nit buildup. In this study the switched temperature irradiation has been employed to conservatively estimate the ELDRS of GLPNP, which provides us with a new insight into the test technique for ELDRS.

The effect of ionization and displacement damage on minority carrier lifetime

Based on 1 MeV electrons and 40 MeV Si ion irradiations, the contribution of ionization and displacement damage to the decrease in the minority carrier lifetime of gate controlled lateral PNP (GLPNP) transistors is investigated by gate sweeping (GS) technique. Molecular hydrogen is employed to increase the ionization radiation sensitivity and help to understand the relationship between the minority carrier lifetime and ionization damage. Experimental results show that 1 MeV electrons mainly induce ionization damage to GLPNP transistors, 40 MeV Si ions primarily produce displacement defects in silicon bulk. For 40 MeV Si ions, with increasing the irradiation dose, the densities of interface trap and oxide charge are almost no change, the minority carrier lifetime obviously decreases. The decrease of the minority carrier lifetime is due to bulk traps induce by 40 MeV Si ions. For 1 MeV electrons, with increasing the irradiation dose, the densities of interface trap and oxide charge for the GLPNP with and without soaked in H2 increase, and the minority carrier lifetime decreases. Compared with the GLPNP transistors without soaking in H2, the density of the interface traps the irradiated GLPNP transistors by 1 MeV electrons and soaked in H2 are larger and the minority carrier lifetime is lower. Therefore, both ionization and displacement damage can induce the decreases in the minority carrier lifetime including bulk minority carrier lifetime and surface minority carrier lifetime.

Temperature-Compensated $\beta$ -Multiplier Current Reference Circuit

This brief presents the new simple schematic for the temperature stable current references based on the well-known $\boldsymbol {\beta }$ -multiplier circuit. The proposed reference utilizes only four MOS transistors and two lateral PNP transistors, which are usually available in standard CMOS technologies along with one well resistor. The temperature-compensation technique has a low process dependence and needs no trimming. However, resistor trimming can be used to precisely set the output current value. The circuit implementation of the proposed technique was fabricated in a standard 0.35- ${\mu }\text{m}$ CMOS process to source a 16- ${\mu }\text{A}$ current. The digital calibration circuit allows setting of the output current in 32 100 nA-steps. The proposed current reference achieves the supply sensitivity of several %/V without the use of the external bandgap voltage reference for the supply regulation. The measured temperature coefficient is 105 ppm/°C over the temperature range from 0 to 110 °C.

Evolution of Activation Energy of Interface Traps in LPNP Transistors Characterized by Deep-Level Transient Spectroscopy

The emission of charge carriers from the interface traps as a function of irradiation dose and bias voltage is investigated in terms of Poole–Frenkel effect (PFE) used by deep-level transient spectroscopy (DLTS). The electrical properties in lateral PNP (LPNP) transistors caused by Co60 gamma-ray radiation are measured in situ during irradiation, showing that the interface traps give the main contribution to the excess base current of LPNP transistors. Based on the DLTS results, with increasing irradiation dose, the density of the charged positive interface traps at a given bias voltage increases. This causes an increase in the electric-field strength in the space-charge region and a decrease in the activation energy of interface traps and an increase in the emission rate of charge carriers from the interface traps, showing a similar feature to the classical PFE. However, the charge sign of the interface traps changes from negative to positive, which is different to the classical PFE, and thus displays a new mode of PFE. In order to confirm this conclusion, various bias conditions are employed during DLTS measurements. With decreasing the reverse bias, the electric-field strength increases, leading to an obvious decrease in activation energy of the interface traps and increase in emission rate of charge carriers. Moreover, the interface traps are shown to be uniformly located at the Si/SiO2 interface, and the uniformly distributed interface traps give the new PFE mode, which is independent of the position in depletion layer.

Dependence of Ideality Factor in Lateral PNP Transistors on Surface Carrier Concentration

The influence of surface carrier concentration on the ideality factor of excess base current ( $\Delta I_{B}$ ) in gated lateral PNP (GLPNP) bipolar junction transistors (BJTs) induced by 1-MeV electrons is investigated. $\Delta I_{B}$ in LPNP BJTs is impacted by the surface carrier density and radiation-induced interface traps. In GLPNP BJTs, the surface carrier concentration can be controlled by the voltage applied to a gate over the base region. The ideality factor changes after irradiation, and its dependence on emitter-base voltage ( $V_{\mathrm {EB}}$ ) is a function of gate voltage. For the irradiated devices, as the gate voltage decreases from +20 to −5 V, the ideality factor for excess base current changes from a single slope to two-slope behavior. The majority carrier concentration at the surface of the base, controlled by the gate voltage, impacts the excess base current and its ideality factor.

Radiation Resistance of Fluorine-Implanted PNP Using Gated-Controlled Lateral PNP Transistor Structure

The radiation damage responses of fluorinated and non-fluorinated lateral PNP transistors are studied with specially designed gated-controlled lateral PNP transistors that allow for the extraction of the oxide trapped charge (Not) and interface trap (Nit) densities. All the samples are exposed in the Co-60γ ray with the dose rate of 0.5 Gy(Si)/s. After the irradiation, the buildup of Not and Nit of the samples with total dose is investigated by the gate sweep test technique. The results show that the radiation resistance of fluorinated lateral PNP transistors is significantly enhanced compared with the non-fluorinated ones.

The base current broadening effect and charge separation method of gate-controlled lateral PNP bipolar transistors

In order to study the total dose effect and hardness assurance technology for the bipolar devices, we have designed and fabricated different gate-controlled lateral PNP bipolar transistors by various technologies, and preformed 60Co-γ low-dose rate irradiation. The test results show that: 1) Irradiation characteristics of the gate-controlled bipolar transistor are strongly dependent on the fabrication technology, and the passivation layer has a great influence on the irradiation response of the device. The device with a passivation layer will have more interface traps in ionizing radiation environments, and its resistance to ionizing irradiation is greatly weakened. 2) A domestic gated-controlled lateral PNP transistor exhibited a peak current broadening effect at low-dose rate irradiation. In this paper, we analyze the mechanism of the broadening effect, and put forward a new separation method for reducing the base current broadening effect, which not only provides the basis for the design of hardened devices, but also a powerful tool for the study of the enhanced low-dose rate sensitivity of the bipolar device.

A 20–40 MHz low-power clock oscillator with open-loop frequency calibration and temperature compensation

In this paper, a 20–40 MHz low-power clock oscillator is presented to provide the frequency reference in data interface applications. The frequency source is referenced to a frequency-calibrated and temperature-compensated 2.5 GHz LC VCO that is implemented with a bondwire inductor. Class-C type VCO is adopted in order to improve the phase noise and reduce the current consumption. A full digital frequency calibration circuit is proposed to cover the wide output frequency range minimizing the frequency variation. External crystal oscillator (REF_CLK) is used only for the absolute frequency calibration at the initial programming stage and is not needed after the programming stage. On the other hand, temperature compensation is performed in an analogue way by controlling the varactor in the LC VCO. This chip is fabricated using 0.18-µm CMOS with the option of lateral PNP transistor. Lateral PNP transistors are used in the temperature compensation circuits. It can be implemented laterally in standard CMOS process. The power consumption is 4.8 mW from a 1.8 V supply. The accuracy of the frequency is ±58 ppm from −20°C to 80°C. The nominal phase noise at 1 MHz and period jitter is −122 dBc/Hz and 2 ps, respectively, when the output frequency is 25 MHz.

Power lateral pnp transistor operating with high current density in irradiated voltage regulator

The operation of power lateral pnp transistors in gamma radiation field was examined by detection of the minimum dropout voltage on heavily loaded low-dropout voltage regulators LM2940CT5, clearly demonstrating their low radiation hardness, with unacceptably low values of output voltage and collector-emitter voltage volatility. In conjunction with previous results on base current and forward emitter current gain of serial transistors, it was possible to determine the positive influence of high load current on a slight improvement of voltage regulator LM2940CT5 radiation hardness. The high-current flow through the wide emitter aluminum contact of the serial transistor above the isolation oxide caused intensive annealing of the positive oxide-trapped charge, leading to decrease of the lateral pnp transistor's current gain, but also a more intensive recovery of the small-signal npn transistors in the control circuit. The high current density in the base area of the lateral pnp transistor immediately below the isolation oxide decreased the concentration of negative interface traps. Consequently, the positive influence of the reduced concentration of the oxide-trapped charge on the negative feedback reaction circuit, together with the favourable effect of reduced interface traps concentration, exceeded negative influence of the annealed oxide-trapped charge on the serial pnp transistor's forward emitter current gain.

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -138°C, no damage occurs until devices are warmed to temperatures above -50°C. After warm-up, subsequent cooling shows that damage is then present at low temperature, although it is much less than for room temperature irradiation. This can be explained by the temperature dependence of dispersive transport in the continuous-time-random-walk model, along with the reduction in charge yield at low temperature. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

Minimum dropout voltage on a serial pnp transistor of a moderately loaded voltage regulator in a gamma radiation field

The main examined value in an experiment performed on moderately loaded voltage regulators was the serial pnp transistor?s minimum dropout voltage, followed by the data on the base current and forward emitter current gain. Minimum dropout voltage decreased by up to 12%, while the measured values of the forward emitter current gain decreased by 20-40% after the absorption of a total ionizing dose of 500 Gy. The oxide trapped charge increased the radiation tolerance of the serial lateral pnp transistor owing to the suppression of interface trap formation above the base area. Current flow through the serial transistor of the voltage regulator had an influence on the decrease in the power pnp transistor?s forward emitter current gain. Due to the operation with a moderate load of 100 mA, loss of emitter injection efficiency was not as important as during the operation with high current density, thus eliminating the negative influence of emitter crowding on the radiation hardness of the voltage regulator. For a moderate load, gain in the negative feedback reaction was enough to keep output voltage in the anticipated range. Only information procured from tests of the minimum dropout voltage on the moderately loaded voltage regulators were not sufficient for unequivocal determination of the examined integrated circuit?s radiation hardness.