Lateral Overflow Integration Capacitor Research Articles

A high dynamic range pixel using lateral overflow integration capacitor and adaptive feedback structure in CMOS image sensors

A high dynamic range pixel using lateral overflow integration capacitor and adaptive feedback structure in CMOS image sensors

An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor.

A lateral overflow integration capacitor (LOFIC) complementary metal oxide semiconductor (CMOS) image sensor can realize high-dynamic-range (HDR) imaging with combination of a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for electron-referred noise floor. However, LOFIC-CMOS image sensor requires a two-channel read-out chain for LCG and HCG signals whose polarities are inverted. In order to provide an area-efficient LOFIC-CMOS image sensor, a one-channel read-out chain that can process both HCG and LCG signals is presented in this paper. An up/down double-sampling circuit composed of an inverting amplifier for HCG signals and a non-inverting attenuator for LCG signals can reduce the area of the read-out chain by half compared to the conventional two-channel read-out chain. A test chip is fabricated in a 0.18 μm CMOS process with a metal-insulator-metal (MIM) capacitor, achieving a readout noise of 130 μVrms for the HCG signal and 1.19 V for the LCG input window. The performance is equivalent to 103 dB of the dynamic range with our previous LOFIC pixel in which HCG and LCG conversion gains are, respectively, 160 μV/e- and 10 μV/e-.

Analysis and Parameter Optimization of High Dynamic Range Pixels for Split Photodiode in CMOS Image Sensors

To achieve high dynamic range and define parameter tradeoff of split photodiode pixel based on lateral overflow integration capacitor (LOFIC) technology, the mechanism of extending dynamic range with split photodiode, dual conversion gain and LOFIC technology was studied. A mathematical model of LOFIC technology combined with split photodiode at different pixel sizes is established, which describes responsivity ratio of dual photodiode, LOFIC, conversion gain, and voltage swing affecting dynamic range by equivalent number of random noise electrons and full-well-capacity (FWC) of pixel. Dynamic range of pixel increases from 131.1dB to 133.6dB as responsivity ratio rises from 12 to 16 with voltage swing of 1V and LOFIC node of 25fF, whereas signal-to-noise ratio (SNR) at dual photodiode signal switching point drops from 28.65dB to 27.23dB for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3~\mu \text{m}\,\,\times 3~\mu \text{m}$ </tex-math></inline-formula> pixel. And dynamic range can reach 141dB when LOFIC node rises to 50fF with responsivity ratio of 18 and SNR at small-size photodiode signal switching point decreased by 0.2dB for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10~\mu \text{m}\,\,\times 10~\mu \text{m}$ </tex-math></inline-formula> pixel. The model shows that dynamic range increases with responsivity ratio and LOFIC, whereas is restricted by SNR at signal switching points. This paper provides a design idea and data reference for the design of high dynamic range (HDR) CMOS image sensors based on split photodiode and LOFIC technology.

Paper] 4.0 μm Stacked Voltage Mode Global Shutter Pixels with Single Exposure High Dynamic Range and Phase Detection Auto Focus Capability

In this paper, two types of 4.0 μm back side illuminated stacked voltage mode global shutter pixels implemented in a prototype CMOS image sensor are reported. One is a pixel with a lateral overflow integration capacitor (LOFIC) to expand the sensor dynamic range and the other is a pixel having dual photodiodes and dual conversion gains which enables the phase detection auto focus capability with single exposure high dynamic range (SEHDR). Thanks to the LOFIC and the dual conversion gain technologies, SEHDR of 90 dB and 77 dB has been achieved in the global shutter mode.

A Global Shutter Wide Dynamic Range Soft X-Ray CMOS Image Sensor With Backside- Illuminated Pinned Photodiode, Two-Stage Lateral Overflow Integration Capacitor, and Voltage Domain Memory Bank

This article presents a prototype $22.4~\mu \text{m}$ pixel pitch global shutter (GS) wide dynamic range (WDR) soft X-ray CMOS image sensor (sxCMOS). Backside-illuminated (BSI) pinned photodiodes with a 45- $\mu \text{m}$ thick Si substrate were introduced for low noise and high radiation hardness to high energy photons. Two-stage lateral overflow integration capacitor (LOFIC) and voltage domain memory bank with high-density Si trench capacitors were introduced for WDR and for GS. The developed sxCMOS achieved maximum 21.9 Me− full well capacity with a single exposure 129 dB dynamic range by GS operation. Over 70% quantum efficiency (QE) toward soft X-ray was successfully achieved. The developed prototype sxCMOS is a step forward toward a 4 M pixel detector system to be utilized in next-generation synchrotron radiation facilities and X-ray free-electron lasers.

An Optical Filter-Less CMOS Image Sensor with Differential Spectral Response Pixels for Simultaneous UV-Selective and Visible Imaging.

This paper presents a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) capable of capturing UV-selective and visible light images simultaneously by a single exposure and without employing optical filters, suitable for applications that require simultaneous UV and visible light imaging, or UV imaging in variable light environment. The developed CIS is composed by high and low UV sensitivity pixel types, arranged alternately in a checker pattern. Both pixel types were designed to have matching sensitivities for non-UV light. The UV-selective image is captured by extracting the differential spectral response between adjacent pixels, while the visible light image is captured simultaneously by the low UV sensitivity pixels. Also, to achieve high conversion gain and wide dynamic range simultaneously, the lateral overflow integration capacitor (LOFIC) technology was introduced in both pixel types. The developed CIS has a pixel pitch of 5.6 µm and exhibits 172 µV/e− conversion gain, 131 ke− full well capacity (FWC), and 92.3 dB dynamic range. The spectral sensitivity ranges of the high and low UV sensitivity pixels are of 200–750 nm and 390–750 nm, respectively. The resulting sensitivity range after the differential spectral response extraction is of 200–480 nm. This paper presents details regarding the CIS pixels structures, doping profiles, device simulations, and the measurement results for photoelectric response and spectral sensitivity for both pixel types. Also, sample images of UV-selective and visible spectral imaging using the developed CIS are presented.

A 120-ke- Full-Well Capacity 160-µV/e- Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor.

In this paper, a prototype complementary metal-oxide-semiconductor (CMOS) image sensor with a 2.8-μm backside-illuminated (BSI) pixel with a lateral overflow integration capacitor (LOFIC) architecture is presented. The pixel was capable of a high conversion gain readout with 160 μV/e− for low light signals while a large full-well capacity of 120 ke− was obtained for high light signals. The combination of LOFIC and the BSI technology allowed for high optical performance without degradation caused by extra devices for the LOFIC structure. The sensor realized a 70% peak quantum efficiency with a normal (no anti-reflection coating) cover glass and a 91% angular response at ±20° incident light. This 2.8-μm pixel is potentially capable of higher than 100 dB dynamic range imaging in a pure single exposure operation.

A wide dynamic range CMOS image sensor with 200–1100 nm spectral sensitivity and high robustness to UV right exposure

A highly UV-light sensitive and sensitivity robust CMOS image sensor with a wide dynamic range (DR) was developed and evaluated. The developed CMOS image sensor includes a lateral overflow integration capacitor in each pixel in order to achieve a high sensitivity and a wide DR simultaneously. As in-pixel photodiodes (PDs), buried pinned PDs were formed on flattened Si surface. The PD has a thin surface p+ layer with a steep dopant concentration profile to form an electric field that drifts photoelectrons to the pinned n layer. This structure improves UV-light sensitivity and its stability. In addition, a buried channel source follower driver was introduced to achieve a low pixel noise. This CMOS image sensor was fabricated by a 0.18-µm 1-polycrystalline silicon 3-metal CMOS process technology with buried pinned PD. The fabricated image sensor has a high sensitivity for 200–1100 nm light wave band, high robustness of sensitivity and dark current toward UV-light exposure and a wide DR of 97 dB. In this paper, the PD structures, the circuit, the operation sequence and the measurement results of this CMOS image sensor are discussed.

A 2.8 µm Pixel-Pitch 55 ke- Full-Well Capacity Global-Shutter Complementary Metal Oxide Semiconductor Image Sensor Using Lateral Overflow Integration Capacitor

In this paper, a global-shutter complementary metal oxide semiconductor (CMOS) image sensor using lateral overflow integration capacitor (LOFIC) in each pixel without trade-offs between full-well capacity (FWC) and dark current and between FWC and pixel size has been demonstrated. Because the FWC is determined only by LOFIC, a photodiode (PD) and storage diffusion capacitor (SD) are designed focusing on achieving low dark current performance especially. A 2.8 µm pixel pitch Bayer-RGB color CMOS image sensor with the pinned diffusion capacitor for the storage node was fabricated and achieved both 83.3 e-/s at the PD and 58.3 e-/s at the SD dark current at 60 °C and about 55 ke- full well capacity. A high resolution performance, a high FWC performance and a low dark current performance were simultaneously achieved in this image sensor.

Pixel Scaling in Complementary Metal Oxide Silicon Image Sensor with Lateral Overflow Integration Capacitor

Two wide dynamic range (DR) complementary metal oxide silicon (CMOS) image sensors (CIS) with lateral overflow integration capacitor (LOFIC) have been developed in order to scale down the pixel size. A checker-pattern CIS has achieved high area-efficiency for the full well capacity (FWC) by introducing the rectangle structure and placing the color-filters and on-chip microlens along the direction at an angle of 45°. A shared two pixels CIS has achieved small pixel pitch by introducing a lateral overflow gate that overflows over-saturated photoelectrons from the photodiode to the LOFIC directly. These CISs were fabricated using the 0.18-µm 2-polycrystalline 3-metal CMOS technology with buried-pinned-photodiode process and achieved the high FWC, low noise, wide DR and high resolution performances. These structures are effective for obtaining the small pixel size with the advantageous characteristics of LOFIC CIS. In this paper, these structures, operation methods and measurement results of these CISs have been discussed.

White–Red–Green–Blue Lateral Overflow Integration Capacitor Complementary Metal–Oxide–Semiconductor Image Sensor with Color-Independent Exposure and Widely-Spectral High Sensitivity

A high sensitivity white–red–green–blue (WRGB) complementary metal–oxide–semiconductor (CMOS) image sensor is proposed with color-independent saturation exposure based on lateral overflow integration capacitor (LOFIC) architecture. In case of conventional WRGB image sensors, the W pixels saturate in lower illuminance than the other pixels due to the same saturation exposure of all pixels. This WRGB LOFIC CMOS image sensor solves this problem by optimizing the size of LOFICs for each pixel color according to its sensitivity. The white (W) pixels have about 2.3 times higher sensitivity than the green (G) pixels and have 102-dB dynamic range (DR). Moreover, W pixels without infrared (IR) cut filter have high sensitivity for luminance through visible light band to near IR wave band. This image sensor realize that good color reproductivity imaging for the visible waveband and high sensitivity imaging for a wide waveband by one image sensor.

A Complementary Metal–Oxide–Semiconductor Image Sensor with 2.0 e- Random Noise and 110 ke- Full Well Capacity and Noise Measurement of Pixel Transistors Using Column Source Follower Readout Circuits

A low noise complementary metal–oxide–semiconductor (CMOS) image sensor without degradation of saturation performance has been developed by using column amplifiers of the gains of about 1.0 in a lateral overflow integration capacitor technology. The 1/4-in., 4.5-µm pitch, 800H×600V pixels CMOS image sensor fabricated by a 0.18-µm 2-poly 3-metal CMOS technology including a buried pinned photo-diode structure has achieved fully linear response, 0.98 column readout gain, 104-µV/e- conversion gain, 2.0-e- total random noise, 110,000-e- full well capacity and 95-dB dynamic range in one exposure. Moreover, the random noise of the developed readout circuits has been reduced to 0.5-e- without degradation of saturation performance. As a result, the behaviors of pixel noises have been accurately measured. Operating condition dependency of the random noise generated by pixel transistors has been measured by using the developed readout circuits. In addition, considering the result of the measurements, we optimize pixel operating condition.

イメージセンシング技術とその応用 画素容量・列容量電荷電圧変換を組合せた多重露光線形応答広ダイナミックレンジＣＭＯＳイメージセンサ

We discuss the operation methods for keeping a high S/N ratio at all switching points in multiple exposures and for shorting the total integration time of a wide dynamic range (DR) lateral overflow integration capacitor (LOFIC) CMOS image sensor that combines electric-charge voltage conversions in a pixel and a column capacitor. We have used these methods on a color LOFIC CMOS image sensor. This sensor had a pixel pitch of 5.6-um and the number of effective pixels was 800 (H) x 600 (V). It was made by using 0.18-um 2P3M CMOS technology. Fully linear responses were obtained, as well as a DR of 207 dB. Furthermore, the S/N ratio was 26-dB for the image of 18% gray card at all the switching points between the multiple exposures. The total exposure time was1/13-sec and was obtained by three photoelectric conversion operations at FD and LOFIC capacitors and one photoelectric conversion operation in the column capacitor.

横型オーバフロー蓄積容量を用いたＣＭＯＳイメージセンサの画素縮小化技術

The relationship between the resolution and pixel pitch considering the optical diffraction principally caused by the lens circle aperture is discussed for the image sensor required to secure a high SNR and full well capacity for each pixel. The light diffraction of some high luminance patterns was calculated. We discuss the results for the optimization methodology of pixel pitch scaling considering the influence of the light diffraction. The performance of a CMOS image sensor with shared and small pixels and lateral overflow integration capacitor was developed based on our results. A CMOS image sensor consisting of 1/3.3 inch optical format, 3-μm pixel pitch and 1280 (H) × 960 (V) pixels was fabricated Using a 0.18-μm 2P3M CMOS technology with a buried pinned photodiode process. The sensor achieved 84μV/e- photo-electric conversion gain, 6.9×104e- full well capacity and 90 dB dynamic range in one exposure.

Optimum Design of Conversion Gain and Full Well Capacity in CMOS Image Sensor With Lateral Overflow Integration Capacitor

An optimum design theory to clarify a possible limit of achieving both high conversion gain (CG) and full well capacity (FWC) at the same time in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) in a pixel is discussed. The possible limit of both high CG and high FWC is theoretically derived from a signal-to-noise-ratio (SNR) formula at a switching point from a low light signal (S1) to a bright one (S2). Based on this theory, a 1/4-in VGA-format 5.6-mum-pixel-pitch CMOS image sensor has been fabricated through a 0.18-mum 2P3M CMOS technology. A high-quality wide-dynamic-range image sensing has been demonstrated with no significant visible noise, achieving over 32 dB of SNR for an 18% gray card.

A 1.9 $e^{-}$ Random Noise CMOS Image Sensor With Active Feedback Operation in Each Pixel

A 1.9 e- random noise CMOS image sensor has been developed by applying an active feedback operation (AFO), which uses a capacitive feedback effect to floating diffusion (FD) by a gate-source capacitance of a pixel source follower (SF), in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) technology. It is described that the AFO is suitable for CMOS image sensors with LOFIC because the design of the full well capacity and the FD can be independently optimized. The AFO theory is found to be explored to a large signal voltage in detail, as well as the conventional analysis of the capacitive feedback effect of the pixel SF for a small signal voltage. A 1/4-in 5.6- mum-pitch 640(H) times 480(V) pixel sensor chip in a 0.18-mum two-poly-Si three-metal CMOS technology achieves about 1.7 times the sensitivity with AFO compared with the case where the feedback operation is not positively used, resulting in an input-referred conversion gain of 210 muV/e- and an input-referred noise of 1.9 e-. A high well capacity of 130 000 e- is also achieved.

A Very Low Dark Current Temperature-Resistant, Wide Dynamic Range, Complementary Metal Oxide Semiconductor Image Sensor

A very low dark current (VLDC) temperature-resistant approach which best suits a wide dynamic range (WDR) complementary metal oxide semiconductor (CMOS) image sensor with a lateral over-flow integration capacitor (LOFIC) has been developed. By implementing a low electric field photodiode without a trade-off of full well-capacity, reduced plasma damage, re-crystallization, and termination of silicon–silicon dioxide interface states in the front end of line and back end of line (FEOL and BEOL) in a 0.18 µm, two polycrystalline silicon, three metal (2P3M) process, the dark current is reduced to 11 e-/s/pixel (0.35 e-/s/µm2: pixel area normalized) at 60 °C, which is the lowest value ever reported. For further robustness at low and high temperatures, 1/3-in., 5.6-µm pitch, 800×600 pixel sensor chips with low noise readout circuits designed for a signal and noise hold circuit and a programmable gain amplifier (PGA) have also been deposited with an inorganic cap layer on a micro-lens and covered with a metal hermetically sealed package assembly. Image sensing performance results in 2.4 e-rms temporal noise and 100 dB dynamic range (DR) with 237 ke- full well-capacity. The operating temperature range is extended from -40 to 85 °C while retaining good image quality.

High Sensitivity Dynamic Range Enhanced Complementary Metal–Oxide–Semiconductor Imager with Noise Suppression

In a high sensitivity complementary metal–oxide–semiconductor (CMOS) image sensor featuring a high conversion gain floating diffusion (FD) with a lateral overflow integration capacitor (LOFIC) in a pixel, the methods of the feedback noise suppression and the FD dark current reduction are discussed. The noise floor is found to be suppressed by introducing a small FD capacitance with the reduced feedback capacitance of a pixel source follower in accordance with a noise feedback theory. The reduction of the full well capacity due to the small FD capacitance causes the reduced tolerance for the FD dark current at the switching point from a low light signal (S1) to a bright light signal (S2). However it is solved by the reduction of the electric field concentrations at the FD in conjunction with the LOFIC capacitance optimization. A 1/4 in. video graphics array (VGA) format CMOS image sensor fabricated through 0.18 µm two-poly three-metal process demonstrates both 2.2 e- rms noise floor and an invisible signal-to-noise (S/N) ratio degradation at the S1/S2 switching point under 2 s integration time while the full well capacity is extended up to 100 ke-.

A 200-$\mu$V/e$^{-}$ CMOS Image Sensor With 100-ke$^{-}$ Full Well Capacity

A high-sensitivity CMOS image sensor keeping a high full-well capacity has been developed by introducing a new pixel having a small floating diffusion (FD) capacitance connected to a lateral overflow integration capacitor (LOFIC) through a MOS switch. The conceptual advantage of the small FD approach over conventional column amplifier approaches is compared and demonstrated. To ensure both the high sensitivity and the high full-well capacity, the low-light and the bright-light signals (S1 and S2) are output and reproduced without a visible SNR degradation at the S1/S2 switching point. As the most critical problem, the increase of the conversion gain variation in this approach is suppressed by applying a self-aligned offset structure to the small FD. A 1/4-in VGA format CMOS image sensor fabricated through 0.18-mum 2P3M process achieves 2.2-e- rms noise floor with 200-muV/e- conversion gain and 100-ke- full-well capacity.

A Sensitivity and Linearity Improvement of a 100-dB Dynamic Range CMOS Image Sensor Using a Lateral Overflow Integration Capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.