Optimum Design of Conversion Gain and Full Well Capacity in CMOS Image Sensor With Lateral Overflow Integration Capacitor

Abstract

An optimum design theory to clarify a possible limit of achieving both high conversion gain (CG) and full well capacity (FWC) at the same time in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) in a pixel is discussed. The possible limit of both high CG and high FWC is theoretically derived from a signal-to-noise-ratio (SNR) formula at a switching point from a low light signal (S1) to a bright one (S2). Based on this theory, a 1/4-in VGA-format 5.6-mum-pixel-pitch CMOS image sensor has been fabricated through a 0.18-mum 2P3M CMOS technology. A high-quality wide-dynamic-range image sensing has been demonstrated with no significant visible noise, achieving over 32 dB of SNR for an 18% gray card.