Lateral Insulated Gate Bipolar Transistor Research Articles

Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor: Current Technologies and Prospects

Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor: Current Technologies and Prospects

Unipolar-Turn-Off Lateral Insulated-Gate Bipolar Transistor With On-Chip Biasing Circuit for Injection Control

Unipolar-Turn-Off Lateral Insulated-Gate Bipolar Transistor With On-Chip Biasing Circuit for Injection Control

Improvement in U-Shaped Channel SOI Lateral IGBT for Wider Reverse Bias Safe Operating Area

In this article, the inductive turn-off failure mechanism of U-shaped channel silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) under high-voltage and high-current is investigated by experiments and numerical simulations. First, the measured turn-off waveforms before and after failure are compared to infer the cause of the failure. Then, the failure is reproduced by calibrated three-dimensional simulations using Sentaurus TCAD. According to the simulation and measured results, the turn-off failure is resulted from the high impact ionization in the bird’s beak region. To reveal the failure mechanism, the turn-off failure process is divided into two phases. In phase I, the electrons generated by drastic impact ionization in the bird’s beak region act as the base current to keep the operation of parasitic PNP transistor after channel pinching off. In phase II, the parasitic NPN transistor is activated due to the hole current amplified by PNP, and thus, turn-off failure occurs. Based on the revealed turn-off failure mechanism, an improved U-shaped channel SOI-LIGBT with a P-top is proposed. The P-top is arranged in the bird’s beak region to reduce the impact ionization rate. The measured results demonstrate that no failure occurs when the improved device turns off under high-voltage and high-current conditions. Compared with the conventional U-shaped channel SOI-LIGBT, the improved device obtains 275% and 23% improvements in turn-off current at a bus voltage of 450 V and reverse bias safe operation area, respectively.

A novel double RESURF SOI-LIGBT with dynamic avalanche immunity and low losses

A novel, trench gates, double reduced surface field, lateral insulated gate bipolar transistor based on silicon-on-insulator (SOI-LIGBT) is proposed and investigated. A p-top layer connected to the emitter via two series diodes and n-rings surrounding the bottom of trench gates are used to reduce the on-state voltage drop (V CE(sat)) and turn-off loss (E off). A deep trench with a p-ring is introduced to form a gate-drain shorted positive channel metal oxide semiconductor, which can automatically raise the potential of the p-ring during turn-off so as to enhance the dynamic avalanche immunity. Besides, the deep trench with a p-ring can shield the high electric field from n-rings at the blocking state, which avoids the breakdown of n-rings. Simulation results indicate that the proposed LIGBT can be safely turned off even under a bus voltage equal to the breakdown voltage (V B), and V CE(sat) under E off = 1 mJ cm−2 can be 24% lower than that of the conventional LIGBT.

Four Hybrid Gates SOI Lateral Insulated Gate Bipolar Transistor With Improved Carrier Controllability

Four Hybrid Gates SOI Lateral Insulated Gate Bipolar Transistor With Improved Carrier Controllability

Influence of Termination Isolation Deep-Oxide Trenches on Short-Circuit Capability in Silicon-On-Insulator Lateral IGBT

Termination isolation deep-oxide trenches (TITs) are inserted in the emitter side of silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) for electrical isolation. TITs have unstudied effect on electrical characteristics of SOI-LIGBT. In this article, the influence of location and electrical potential of TITs on short-circuit characteristics is investigated. SOI-LIGBTs with different TITs are fabricated and measured, and then, detailed calibrated TCAD simulations are carried out to elucidate the influence of TITs. By adjusting the location of TITs, the electrical potential distribution in the emitter side is reshaped, and the electrical potential at the end of inversion channel ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{ch}}$ </tex-math></inline-formula> ) is lowered. A lower saturation current is achieved due to the reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{ch}}$ </tex-math></inline-formula> . TITs with negative electrical potential can attract more holes in the short-circuit condition, which can suppress the activation of parasitic n-p-n transistor. Both reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text{sat}}$ </tex-math></inline-formula> and suppressed latch up can significantly improve short-circuit withstanding time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{\text{SC}}$ </tex-math></inline-formula> ). By optimizing location and electrical potential of TIT, SOI-LIGBT can achieve 69.1% increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{\text{SC}}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{CE}} = 400$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{GE}} = 15$ </tex-math></inline-formula> V without influencing other electrical characteristics.

A Silicon-On-Insulator Lateral IGBT With Segmented Trenches for Improving Short-Circuit Withstanding Capability

For the first time, a silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) featuring segmented deep oxide trenches (SDOTs) is proposed, which aims to suppress the saturation current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {sat}}$ </tex-math></inline-formula> ) and enhance the short-circuit withstanding capability. SDOTs, refilled by the polysilicon and shorted to the emitter electrode, are inserted in the region nearby the inversion channel. In the ON-state, the electric potential at the channel end can be modified and effectively lowered by the grounded SDOTs, which indicates the reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {sat}}$ </tex-math></inline-formula> and prolonged short-circuit withstanding time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{\text {SC}}$ </tex-math></inline-formula> ). Compared with the conventional SOI LIGBT, the proposed SOI LIGBT achieves a 49.5% decrease in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {sat}}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {CE}} = {10}$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GE}} = {15}$ </tex-math></inline-formula> V, and a 406% increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{\text {SC}}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {CE}} = {400}$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GE}} = {15}$ </tex-math></inline-formula> V.

Double-Gate RESURF Lateral Insulated Gate Bipolar Transistor With Built-In p-Channel MOSFET for Active Conductivity Modulation Control Throughout Drift Region

A double-gate RESURF lateral IGBT (DGR-LIGBT) with build-in p-channel MOSFET (p-MOSFET) is proposed and studied by numerical TCAD simulations. In the conventional LIGBTs, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ON}}$ </tex-math></inline-formula> is reduced by conductivity modulation in drift region. However, the stored minority carriers lead to high turn-off lose ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {OFF}}$ </tex-math></inline-formula> ). In the proposed DGR-LIGBT, the RESURF region is connected to the p-body via the built-in p-MOSFET. The primary gate switches the DGR-LIGBT between on- and off-states. In the on-state, a positive auxiliary gate voltage is applied to turn off the p-MOSFET; the RESURF region is disconnected from the p-body. Thus, the DGR-LIGBT works in fully modulated state and maintains a low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ON}}$ </tex-math></inline-formula> . Before the turn-off transient, the auxiliary gate voltage is pre-switched to a negative voltage to turn on the p-MOSFET, which electrically connects the RESURF region to the grounded p-body and extracts holes in the entire drift region. Therefore, the conductivity modulation throughout the drift region is suppressed, resulting in low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {OFF}}$ </tex-math></inline-formula> .

Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench

A lateral insulated gate bipolar transistor (LIGBT) based on silicon-on-insulator (SOI) structure is proposed and investigated. This device features a compound dielectric buried layer (CDBL) and an assistant-depletion trench (ADT). The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that, under the same breakdown voltage (BV) condition, allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers. Reducing their numbers helps in fast-switching. Furthermore, the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel. The simulation results show that the BV of the proposed LIGBT is increased by 113% compared with the conventional SOI LIGBT of the same length L D. Contrastingly, the length of the drift region of the proposed device (11.2 μm) is about one third that of a traditional device (33 μm) with the same BV of 141 V. Therefore, the turn-off loss (E OFF) of the CDBL SOI LIGBT is decreased by 88.7% compared with a conventional SOI LIGBT when the forward voltage drop (V F) is 1.64 V. Moreover, the short-circuit failure time of the proposed device is 45% longer than that of the conventional SOI LIGBT. Therefor, the proposed CDBL SOI LIGBT exhibits a better V F–E OFF tradeoff and an improved short-circuit robustness.

All-directional Electrostatic-discharge Protection Circuit with High Area-efficiency

This paper proposes a design for a wholechip all-directional electrostatic-discharge (ESD) protection circuit using a resistor-capacitor (RC) lateral insulated-gate bipolar transistor (LIGBT)-based 12 V power clamp and a silicon-controlled rectifier (SCR)-based 12 V input/output (I/O) clamp. The RC LIGBT-based power clamp detects pulses through an ESD detection circuit and applies a bias to the gate. Therefore, the proposed power clamp does not have snapback curve and has a low impedance during an ESD event. In addition, the structural characteristics of the proposed I/O clamp enable it to provide discharge paths for all four ESD discharge modes (PS, PD, NS, ND), and the clamp is more area efficient than conventional ESD protection circuits composed of gate-grounded n-type metal-oxide-silicon transistors or SCRs. Moreover, because floating regions are inserted in the I/O clamp and the clamp has a high holding voltage, the clamp design is resistant to latch-up, which is a critical drawback of snapback devices. Therefore, the proposed ESD protection circuit can effectively provide highly reliable protection to internal integrated circuits. The proposed circuit was fabricated using a 0.18 ㎛ bipolar-CMOS-DMOS process, and the electrical properties and ESD robustness of the circuit were verified through a transmission line pulse measurement method and human body model surge application tests.

Simulation Study of Novel Trench Gate U-Shaped Channel SOI Lateral IGBTs With Suppressed Gate Voltage Overshoot and Reduced di/dt

The gate voltage overshoot during the turn-on transient in the trench gate U-shaped (TGU) channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is investigated and novel structures are proposed for the first time with numerical simulation in this article. The TGU SOI-LIGBT features two U-shaped trench gates, G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> and G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , connected together. The U-shaped trench for G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> serves as a hole barrier trench. A large number of holes accumulate in the U-shaped region during the turn-on transient because of the U-shaped architecture and the hole-blocking effect of G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The displacement current induced by the nonuniform distributed holes overcharges the gate and leads to high di/dt. In this article, the novel structures (Novel-1 and Novel-2) with G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> partially filled by the polysilicon are proposed for the improvement in gate voltage overshoot while keeping superior turn-on loss ( E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ON</sub> ). The novel structures (Novel-1 and Novel-2) can suppress the hole accumulation and slow down the rising of the electric potential in the silicon region near the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The di/dt can be lowered and the displacement current that overcharges G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> can be effectively shielded. Compared with the conventional TGU structure, the di/dt of the Novel-2 are improved by 56.3% at the same E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ON</sub> of 2.4 mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Novel Snapback-Free SOI LIGBT With Shorted Anode and Trench Barriers

A novel fast-switching silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed and investigated in this article. The proposed device introduces trench barriers (TBs) at the collector end based on shorted anode (SA) structure to eliminate the snapback effect. The introduced TB structure can make the flow path of electron current be compressed and extended when the SA LIGBT is turned on so that the opening of collector p+/n-junction is prior to that of collector n+/n-junction. At the same time, it retains the ability to extract unbalanced electrons when the SA LIGBT is turned off. Through the TCAD simulation, the obtained results show that snapback-free can be realized by changing trench depth and pitch between TB structures. Compared with the separated SA (SSA) LIGBT, the forward voltage drop of the proposed LIGBT is reduced by 13.9% with snapback-free and much shorter collector region, which also retains the ability to extract unbalanced electrons. Thus, under the same forward voltage drop of 1.49 V, the turn-off time, and loss of the proposed LIGBT is 20.3% and 21.1% lower than those of the conventional (Conv.) LIGBT, respectively. In general, the tradeoff between turn-off time and forward voltage drop of the proposed LIGBT has much better performance.

4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide range of snapback phenomena is triggered for 4H-SiC-based ESD protection devices owing to a high critical electric field. In this study, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed. The proposed ESD protection device minimizes the effective base region of the NPN parasitic bipolar transistor to the gate length based on the internal SCR operation of the LIGBT. It also adjusts the emitter injection efficiency of the PNP parasitic bipolar transistor by introducing a segment topology and inserting an additional implant area. Consequently, the proposed ESD protection device significantly improves the wide range of snapback phenomena occurring in the 4H-SiC materials. A conventional SCR, the LIGBT, and the proposed protection device were fabricated using the 4H-SiC process under the same condition, and their electrical characteristics were comparatively analyzed using a transmission-line pulse system. Moreover, its high-temperature reliability was evaluated at 300–500 K to examine the compatibility with 4H-SiC devices and circuits that require a relatively high-temperature operation.

Novel Low Loss LIGBT With Assisted Depletion N-Region and P-Buried Layer

A novel low loss lateral insulated gate bipolar transistor (LIGBT) with high voltage level is designed and studied in this paper, and is proposed with assisted depletion N-region (AD) and P-buried layer (PB) in the bulk Si substrate, named PBAD LIGBT. The proposed PBAD LIGBT utilizes the idea of electric field modulation (EFM) to greatly improve the breakdown voltage, which optimizes the lateral and longitudinal electric field distribution by introduced high electric field peak. Therefore, compared with conventional (Conv.) LIGBT, the shortened drift length of proposed PBAD LIGBT is beneficial to improve the forward and switching characteristics at the same time, while maintaining the same breakdown characteristics. When the breakdown voltage reaches 360 V, according to the TCAD simulation results, the drift length of proposed PBAD LIGBT is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$20{\mu }\text{m}$ </tex-math></inline-formula> , which is 71.4% shorter than that of Conv. LIGBT of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$70{\mu }\text{m}$ </tex-math></inline-formula> . As a result of shortening drift length, the forward voltage drop and turn-off loss of proposed PBAD LIGBT are reduced by 51.4% and 68.5%, respectively. The simulated trade-off curves show that, proposed PBAD LIGBT achieves significantly improved trade-off performance between turn-off loss and forward voltage drop than that of Conv. LIGBT, including PB LIGBT and AD LIGBT.

Experimental investigation on total-ionizing-dose radiation effects on the electrical properties of SOI-LIGBT

In this paper, the experimental investigation on the electrical properties of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) after total-ionizing-dose (TID) irradiation is presented. We find that the TID irradiation reduces the threshold voltage (Vth), and increases the collector current (ICE) at the same gate voltage (Vg). The raising ICE is mainly attributed to the negative shift of the Vth. However, at the same overdrive voltage (Vov = Vg − Vth), the ICE at small VCE increases and the ICE at high VCE decreases after irradiation. The distinctive response of the out-put characteristics after irradiation is ascribed to the positive trapped charges in the field oxide (FOX) layer and the buried oxide (BOX) layer. The inimitable out-put behavior occurs at whatever the sign of the gate bias voltage during irradiation. The degradation mechanisms of the TID effects on the SOI-LIGBT are further analyzed and confirmed by simulation.

Novel fast-switching LIGBT with P-buried layer and partial SOI* *Project supported by the National Basic Research Program of China (Grant No. 2015CB351906) and the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017).

A novel silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed in this paper. The proposed device has a P-type buried layer and a partial-SOI layer, which is called the BPSOI-LIGBT. Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer, the proposed structure generates two new peaks in the surface electric field distribution, which can achieve a smaller device size with a higher breakdown voltage. The smaller size of the device is beneficial to the fast switching. The simulation shows that under the same size, the breakdown voltage of the BPSOI LIGBT is 26% higher than that of the conventional partial-SOI LIGBT (PSOI LIGBT), and 84% higher than the traditional SOI LIGBT. When the forward voltage drop is 2.05 V, the turn-off time of the BPSOI LIGBT is 71% shorter than that of the traditional SOI LIGBT. Therefore, the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT. In addition, the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.

A snapback-free and high-speed SOI LIGBT with double trenches and embedded fully NPN structure

A novel 600 V snapback-free high-speed silicon-on-insulator lateral insulated gate bipolar transistor is proposed and investigated by simulation. The proposed device features an embedded NPN structure at the anode side, and double trenches together with an N-type carrier storage (N-CS) layer at the cathode side, named DT-NPN LIGBT. The NPN structure not only acts as an electron barrier to eliminate the snapback effect in the on-state within a smaller cell pitch but also provides an extra electron extracting path during the turn-off stage to decrease the turnoff loss (Eoff). The double cathode trenches and N-CS layer hinder the hole from being extracted by the cathode quickly. They then enhance carrier storing effect and lead to a reduced on-state voltage drop (Von). The latch-up immunity is improved by the double cathode trenches. Hence, the DT-NPN LIGBT obtains a superior tradeoff between the Von and Eoff. Additionally, the DT-NPN LIGBT exhibits an improved blocking capability and weak dependence of breakdown voltage (BV) on the P+ anode doping concentration because the NPN structure suppresses triggering the PNP transistor. The proposed LIGBT reduces the Eoff by 55% at the same Von, and improves the BV by 7.3% compared to the conventional LIGBT.

Snapback-free shorted anode LIGBT with controlled anode barrier and resistance* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61604027 and 61704016) and the Fund from Chongqing Technology Innovation and Application Development (Key Industry Research and Development), China (Grant No. cstc2018jszx-cyzd0646).

A novel shorted anode lateral-insulated gate bipolar transistor (SA LIGBT) with snapback-free characteristic is proposed and investigated. The device features a controlled barrier V barrier and resistance R SA in anode, named CBR LIGBT. The electron barrier is formed by the P-float/N-buffer junction, while the anode resistance includes the polysilicon layer and N-float. At forward conduction stage, the V barrier and R SA can be increased by adjusting the doping of the P-float and polysilicon layer, respectively, which can suppress the unipolar mode to eliminate the snapback. At turn-off stage, the low-resistance extraction path (N-buffer/P-float/polysilicon layer/N-float) can quickly extract the electrons in the N-drift, which can effectively accelerate the turn-off speed of the device. The simulation results show that at the same V on of 1.3 V, the E off of the CBR LIGBT is reduced by 85%, 73%, and 59.6% compared with the SSA LIGBT, conventional LIGBT, and TSA LIGBT, respectively. Additionally, at the same E off of 1.5 mJ/cm2, the CBR LIGBT achieves the lowest V on of 1.1 V compared with the other LIGBTs.

A Study on 4H-SiC LIGBT with Dual Emitter for High Voltage Driver IC

This paper describes a lateral insulated gate bipolar transistor (LIGBT) with dual emitter structure in 4H-silicon carbide (4H-SiC). The electrical characteristics of the dual-emitter LIGBT are better than those of the conventional 4H-SiC LIGBT. The dual-emitter structure has an additional emitter between the emitter and the collector in the conventional LIGBT structure. The addition of the emitter can significantly improve forward voltage drop, on-resistance and current driving characteristics. Experimental results show that the 4H-SiC dual-emitter LIGBT has lower forward voltage drop, lower on-resistance and a higher current driving capability than the conventional 4H-SiC LIGBT.

A Novel No Miller Plateau SOI-LIGBT With Low Saturation Current and Improved Switching Performance

This article proposes a new idea to improve the $\text{d}{I}/\text{d}{t}$ and $\text{d}{V}/\text{d}{t}$ controllability of the lateral insulated gate bipolar transistor (LIGBT). By employing an inversion layer thyristor T to enhance the conductivity modulation and applying the startup nMOS M4 with small Miller capacitance, the proposed LIGBT not only realizes low saturation current, but also eliminates the Miller plateau. The simulation results demonstrate that the saturation current with a value of 682 A/cm2 is reduced by 55.5%, and the short-circuit time is improved by 375% in comparison with that of the self-adjust conductivity modulation LIGBT (SCM-LIGBT) silicon-on-insulator LIGBT (SOI-LIGBT). Especially, the $\text{d}{V}/\text{d}{t}$ and $\text{d}{I}/\text{d}{t}$ controllability are improved by 21% and 49%, respectively, since the Miller plateau is basically eliminated.