Lateral DMOS Research Articles

On the Geometrically Dependent Quasi-Saturation and Reduction in Advanced DeMOS Transistors

This paper reveals an early quasi-saturation (QS) effect attributed to the geometrical parameters in shallow trench isolation-type drain-extended MOS (STI-DeMOS) transistors in advanced CMOS technologies. The quasi-saturation effect leads to serious $g_{m}$ reduction in STI-DeMOS. This paper investigates the nonlinear resistive behavior of the drain-extended region and its impact on the particular behavior of the STI-DeMOS transistor. In difference to vertical DMOS or lateral DMOS structures, STI-DeMOS exhibits three distinct regions of the drain extension. A complete understanding of the physics in these regions and their impact on the QS behavior are developed in this paper. An optimization strategy is shown for an improved $g_{m}$ device in a state-of-the-art 28-nm CMOS technology node.

Design of a novel triple reduced surface field LDMOS with partial linear variable doping n-type top layer

A novel triple reduced surface field (RESURF) lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) with partial linear variable doping (LVD) N-type top (N-top) layer is proposed in this paper. Compared with the conventional triple RESURF LDMOS, a partial LVD N-top layer is introduced in the surface of N-well, providing a low on-resistance conduction path and leading to an optimized surface electric field, which alleviates the inherent tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp). With the n-drift region length of 70 μm, the novel triple RESURF LDMOS obtains a high BV of 847 V and a low Ron,sp of 79 mΩ cm2 which are 76 V higher and 46 mΩ cm2 lower than those of the conventional triple RESURF LDMOS. Therefore, the novel triple RESURF LDMOS can greatly improve the tradeoff between BV and Ron,sp. Furthermore, compared with the other existing technologies in the high BV level, the novel triple RESURF LDMOS can achieve a highest figure of merit (FOM, defined as BV2/Ron,sp) of 9.08 MW/cm2 and the conventional RESURF silicon limits are broken.

New folding lateral double diffused metal oxide semiconductor breaking silicon limit with ultra‐low specific on‐resistance

A new lateral double diffused metal oxide semiconductor (LDMOS) is proposed for the first time with the step oxide layer above the folding silicon substrate. Three technologies, including of the electric field modulation effect, majority carrier accumulation, and folding silicon, are applied simultaneously to the proposed LDMOS for improving the trade-off between the breakdown voltage (BV) and specific on-resistance (R on,sp). The majority carrier accumulation layer under the extended gate is formed in the folding silicon substrate during the on-state operation. The high-doping drift region can be depleted completely in the off-state, thanks to an additional electric field modulation, which is analogous to the super junction idea. The uniform lateral electric field has been obtained due to the new electric field peak to improve the trade-off between the BV and R on,sp. The proposed LDMOS shows the R on,sp of 0.32 mΩ cm2 with the BV of 62 V, which has broken the silicon limit relationship with R on,sp of 2.0 mΩ cm2 under the same BV in the conventional LDMOS. This is the previously reported lowest R on,sp with the BV of about 60 V.

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance**Project supported by the National Natural Science Foundation of China (Grant No. 61376080), the Natural Science Foundation of Guangdong Province, China (Grant No. 2014A030313736), and the Fundamental Research Funds for the Central Universities, China (Grant No. ZYGX2013J030).

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson’s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology**Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P– region and two diodes in series. In the on-state with VGD > 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V.

Analytical Modeling for a Novel Triple RESURF LDMOS With N-Top Layer

An analytical model for a novel triple reduced surface field (RESURF) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a low on-resistance n-type top (N-top) layer is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF LDMOS is presented by solving the 2-D Poisson's equation, which can also be applied in single, double, and conventional triple RESURF structures. The vertical and lateral breakdown voltages are formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of the N-top layer (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ntop</sub> ) is derived which can give a guidance for the dose of N-top layer. The triple RESURF LDMOS with a low on-resistance N-top layer is designed and manufactured according to the analytical model. All the analytical results can be well verified by numerical and measured results, showing the validity of the presented model.

Hot-Carrier-Induced On-Resistance Degradation of n-Type Lateral DMOS Transistor With Shallow Trench Isolation for High-Side Application

In this paper, the hot-carrier-induced on-resistance degradation of the n-type lateral DMOS (nLDMOS) transistor with shallow trench isolation (STI) for high-side application has been experimentally investigated. We have found that the dominant on-resistance degradation mechanism of the high-side nLDMOS device (HS-nLDMOS) is the interface state generation at the STI corner. Moreover, the degradation of the on-resistance for high-side application (R on,hs, measured at high drain voltage and high source voltage) is much larger than that for low-side application (R on,ls, measured at low drain voltage and grounded source). This is because the current distribution under the R on,hs state is closer to the damaged STI corner than that under the R on,ls state due to the larger potential difference between the drain and the substrate. Therefore, the on-resistance degradation of the HS-nLDMOS must be measured by using the R on,hs condition, to evaluate the lifetime of the device accurately.

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

We propose a distinct approach to implement a laterally single diffused metal-oxide-semiconductor (LSMOS) FET with only one impurity doped p-n junction. In the LSMOS, a single p-n junction is first created using lateral dopant diffusion. The channel is formed in the p region of the p-n junction and the n region acts as the drift region. Two distinct metals of different work function are used to form the “n+” source/drain regions and “p+” body contact using the charge plasma concept. We demonstrate that the LSMOS is similar in performance to a laterally double diffused metal-oxide-semiconductor (LDMOS) although it has only one impurity doped p-n junction. The LSMOS exhibits a breakdown voltage of ∼50.0 V, an average ON-resistance of 48.7 mΩ-mm2 and a peak transconductance of 53.6 μS/μm similar to that of a comparable LDMOS.

A 600V-Class Partial SOI LDMOS with Step-Doped Drift Region

A 600V-class lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) in partial silicon-on-insulator (PSOI) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped method induces an electric field peak in the surface of the device, which can reduce the surface field in the device and adjust the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance.

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer**Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079) and the Program for New Century Excellent Talents at the University of Ministry of Education of China (Grant No. NCET-11-0062).

An ultra-low specific on-resistance (Ron,sp) oxide trench-type silicon-on-insulator (SOI) lateral double-diffusion metal–oxide semiconductor (LDMOS) with an enhanced breakdown voltage (BV) is proposed and investigated by simulation. There are two key features in the proposed device: one is a U-shaped gate around the oxide trench, which extends from source to drain (UG LDMOS); the other is an N pillar and P pillar located in the trench sidewall. In the on-state, electrons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The Ron,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field (E-field) strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV. The BV of 662 V and Ron,sp of 12.4 mΩ·cm2 are achieved for the proposed UG LDMOS. The BV is increased by 88.6% and the Ron,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS (CT LDMOS), realizing the state-of-the-art trade-off between BV and Ron,sp.

An Improved Quasi-Saturation and Charge Model for SOI-LDMOS Transistors

In this paper, we report an accurate quasi-saturation model and a nodal charge model for silicon-on-insulator lateral double-diffused metal–oxide–semiconductor (SOI-LDMOS) transistors. First, a model of a 2-D SOI resistor under velocity saturation is developed, which is subsequently incorporated into the drift region of an LDMOS transistor to predict the quasi-saturation effect. The gate-voltage dependence of the quasi-saturation current is also modeled. Second, we propose a new nodal charge model to describe the dynamic behavior of the device. Comparisons of modeling results with device simulation data show that the proposed model is accurate over a wide range of bias. Scalability of the model with respect to the length of the drift region under the field oxide is also demonstrated. Finally, the model is validated under device self-heating conditions and by comparing it with the experimental data.

Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal–Oxide–Semiconductor Transistors Using High-k Dielectric

By employing the linear increasing drift region width and the high-k dielectric region, a novel variation of lateral width (VLW) technique is proposed to even the equipotential contour and increase the drift doping concentration, which maximize the breakdown voltage and reduce the specific ON-resistance. The breakdown voltage exceeds 600 Von the VLW lateral double-diffused metal-oxide-semiconductor (LDMOS) with 1-μm silicon-on-insulator layer, 3-μm buried oxide, and 60-μm drift region length. The 3-D simulation indicates that the proposed device increases the breakdown voltage by 140%, while reduces the specific ON-resistance by 50% in comparison with the conventional (CONV) device with the same geometric parameters. Moreover, VLW LDMOS presents the best figure of merit, which is 10, 1.8, and 4.5 times higher than that of CONV, variation of lateral doping, and variation of lateral thickness devices, respectively.

Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage

A novel Lateral Double-diffusion Metal Oxide Semiconductor (LDMOS) is proposed to enhance its breakdown voltage (BV) and reduce specific ON-resistance (RON,sp), and its mechanism is investigated by simulation. It features a junction field plate (JFP) at surface and an N+ floating layer (NFL) in the P-substrate. The lateral variation doping JFP not only modulates the surface electric field (E-field) distribution to improve the BV, but also allows a high N-drift doping concentration and thus reduces the RON,sp owing to the charge compensation effect between the N-drift region and P region in the JFP in the OFF-state. The heavily doped NFL is not fully depleted and thus is an equipotential layer in the lateral direction. It thus reshapes the equipotential contours at both the source and drain sides, avoiding the E-field concentration and premature breakdown under the drain; moreover, the additional vertical diode is induced between the NFL and P-sub and it thus extends the depletion width in P-sub, both of which increase the BV. The RON,sp and BV of the JFP-NFL LDMOS is improved by 47% and 63%, respectively, compared with those of a conventional LDMOS at the same dimension. The JFP-NFL LDMOS achieves a superior tradeoff between RON,sp and BV to the different single-, double-, and triple-REduced SURface Field LDMOSFETs with planar technology.

Driving circuit with high accuracy and large driving capability for high voltage buck regulators

This paper presents a novel driving circuit for the high-side switch of high voltage buck regulators. A 40 V P-channel lateral double-diffused metal—oxide—semiconductor device whose drain—source and drain—gate can resist high voltage, but whose source—gate must be less than 5 V, is used as the high-side switch. The proposed driving circuit provides a stable and accurate 5 V driving voltage for protecting the high-side switch from breakdown and achieving low on-resistance and simple loop stability design. Furthermore, the driving circuit with excellent driving capability decreases the switching loss and dead time is also developed to reduce the shoot-through current loss. Therefore, power efficiency is greatly improved. An asynchronous buck regulator with the proposed technique has been successfully fabricated by a 0.35 μm CDMOS technology. From the results, compared with the accuracy of 16.38% of the driving voltage in conventional design, a high accuracy of 1.38% is achieved in this work. Moreover, power efficiency is up to 95% at 12 V input and 5 V output.

Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors.

Modeling of the secondary breakdown in a lateral DMOS transistor by irradiation

Using numerical modeling, we have considered the influence of the design-technological parameters of a lateral DMOS-transistor on the resistance to the effect of a secondary breakdown caused by the action of heavy charged particles. Approaches to the optimization of a DMOS-transistor resistant to the action of heavy charged particles are developed. Comparison of the modeling results of the DMOS-transistor’s robustness with the experimental data has been carried out.

A new high-side and low-side LDMOST with a selective buried layer in the substrate

In this article, a novel low- and high-side lateral double-diffused metal–oxide–semiconductor field-effect-transistor (LDMOST) with an n-type selective buried layer (SBL-LDMOST) in a p-type substrate is presented. When the device operates in the high-side mode, the buried layer prevents vertical punch-through and then the vertical breakdown voltage (BV) is enhanced. When the device operates in the low-side mode, the depleted space-charges in the selective buried layer modulate the bulk electric field and then enhance the substrate to sustain higher reverse voltage. Simulation results show that the low-side BV increases from 585V of the conventional LDMOST to 688V and the high-side BV increases from 962V to 1791V at the same 60μm drift region lengths condition. In addition, when operating in the high-side mode, the drive-current is not alleviated due to drift region immunity from depletion.

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal—oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (Ron.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in Ron.sp by 45.7% simultaneously.

An analytical model for the vertical electric field distribution and optimization of high voltage REBULF LDMOS

In this paper, an analytical model for the vertical electric field distribution and optimization of a high voltage-reduced bulk field (REBULF) lateral double-diffused metal—oxide-semiconductor (LDMOS) transistor is presented. The dependences of the breakdown voltage on the buried n-layer depth, thickness, and doping concentration are discussed in detail. The REBULF criterion and the optimal vertical electric field distribution condition are derived on the basis of the optimization of the electric field distribution. The breakdown voltage of the REBULF LDMOS transistor is always higher than that of a single reduced surface field (RESURF) LDMOS transistor, and both analytical and numerical results show that it is better to make a thick n-layer buried deep into the p-substrate.

Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer

A novel 1200-V ultra-thin partial silicon-on-insulator (PSOI) lateral double-diffusion metal oxide semiconductor (LDMOS) with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed in this paper. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conduction region for majority carriers and a silicon window to improve self-heating effect (SHE). A combination of uniform and linear variable doping (ULVD) profile is utilized in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (Ron,sp) and breakdown voltage (BV). With the n-drift region length of 80μm, the NBL PSOI LDMOS obtains a high BV of 1243V which is improved by around 105V in comparison to the conventional SOI LDMOS with linear variable doping (LVD) profile for the n-drift region (LVD SOI LDMOS). Besides, the 1200-V NBL PSOI LDMOS has a lower maximum temperature (Tmax) of 333K at a power (P) of 1mW/μm which is reduced by around 61K. Meanwhile, Ron,sp and Tmax of the NBL PSOI LDMOS are lower than those of the conventional LVD SOI LDMOS for a wide range of BV.