Lateral Double-diffused Metal-oxide-semiconductor Transistors Research Articles

Design considerations of a novel Triple Oxide Trench Deep Gate LDMOS to improve self‐heating effect and breakdown voltage

In this study, design considerations of a new device structure are presented to improve the self-heating effect (SHE) and the breakdown voltage of the Deep Gate LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor and compared with a conventional LDMOS (C-LDMOS). In this case, triple oxide trenches with an N+ trench are embedded in the drift region. These trenches create additional peaks in the electric field profile, so the electric field is modified. The authors demonstrate that by optimising the trenches, the breakdown voltage of the device increases. Also, a partially buried oxide is used in the proposed structure to create a conduction path that significantly reduces the SHE. Moreover, the results indicate that the specific on-resistance, lattice temperature, and breakdown voltage of the proposed device are improved considerably compared to the C-LDMOS.

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars**Project supported by the National Natural Science Foundation of China (Grant Nos. 61704084 and 61874059).

This paper presents a new silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor transistor (LDMOST) device with alternated high-k dielectric and step doped silicon pillars (HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage (BV) and specific on-resistance (Ron, sp) are obtained. The results indicate that the HKSD device has a higher BV and lower Ron, sp compared to the SD device and HK device.

Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors.

An analytical model for the vertical electric field distribution and optimization of high voltage REBULF LDMOS

In this paper, an analytical model for the vertical electric field distribution and optimization of a high voltage-reduced bulk field (REBULF) lateral double-diffused metal—oxide-semiconductor (LDMOS) transistor is presented. The dependences of the breakdown voltage on the buried n-layer depth, thickness, and doping concentration are discussed in detail. The REBULF criterion and the optimal vertical electric field distribution condition are derived on the basis of the optimization of the electric field distribution. The breakdown voltage of the REBULF LDMOS transistor is always higher than that of a single reduced surface field (RESURF) LDMOS transistor, and both analytical and numerical results show that it is better to make a thick n-layer buried deep into the p-substrate.

Advances in LDMOS Compact Modeling for IC Design: The SP-HV Model and Its Capabilities

Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are key interfaces between digital CMOS circuits and the real analog world; they are widely used in high-voltage and high-current applications, but they can be exceedingly difficult to model accurately. This article reviews recent advances in the compact modeling of LDMOS transistors, with an emphasis on the surface-potential-based high-voltage MOS (SP-HV) model and its capabilities. Detailed physical analysis of experimentally observed complexities in LDMOS behavior are reviewed and the relevance to IC design of the advanced modeling capabilities of SP-HV are detailed.

A Novel Silicon-on-Insulator Super-Junction Lateral-Double-Diffused Metal-Oxide-Semiconductor Transistor with T-Dual Dielectric Buried Layers

A novel silicon-on-insulator (SOI) high-voltage device of super-junction (SJ) lateral-double-diffused metal-oxide-semiconductor transistors (LDMOSTs) with T-dual dielectric buried layers (T-DBLs) is presented. The T-DBLs are formed by the first T-shaped dielectric layer and the second dielectric layer. A lot of holes are accumulated on the top interface of the second dielectric layer, which compensates for the charge imbalance of the surface N and P pillars, thus the substrate-assisted depletion (SAD) effect is eliminated in the new device. The electric field of the second dielectric buried layer, E12, is enhanced by the interface charges, and the breakdown voltage Vbreakdown is increased. E12 = 515 V/μm is obtained in the T-DBL SOI SJ. The Vbreakdown of the new device is increased from 124 V of the conventional SOI SJ to 302 V with a 15 μm length drift region. The specific on-resistance (Ron,sp) of the T-DBL SOI SJ is only 0.00865 Ω·cm2 and the FOM (FOM = V2breakdown/Ron,sp) is 10.54 MW/cm2.

A Novel High-Voltage ($>$ 600 V) LDMOSFET With Buried N-Layer in Partial SOI Technology

A novel lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a buried N-type layer (BNL) in partial silicon-on-insulator (PSOI) is introduced to achieve breakdown voltage (BV) above 600 V and reduce on-resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ). The BNL induces enhanced voltage into the buried oxide layer, which results in higher BV. The higher doping concentration in the BNL can provide more electrons to support higher current and thus reduce on-resistance. The proposed LDMOS transistor with a BNL in PSOI (BNL-PSOI) is analyzed and compared with LDMOS transistors with conventional SOI (CSOI), conventional PSOI (CPSOI), and a BNL in SOI (BNL-SOI) by 2-D numerical simulations. The results indicate that the proposed structure can significantly improve BV up to 660 V and reduce on-resistance by 13.6%-15.5% in comparison to CSOI and CPSOI.

A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop

Received October 5 2009, Revised December 28 2009, Accepted January 22 2010 The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and meas‐urements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the period. A high voltage lateral double diffused metal‐oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the 0.18 µm standard CMOS process, with an AFE core size of 350 µm × 230 µm. The measurement results show that the DPLL, using a demodulator output sig‐nal, generates a constant 1.695 MHz clock during the period of the 100% ASK signal. Keywords: Radio frequency identification, Analog front end, Amplitude shift keying, Digital phase locked loop 1. INTRODUCTION Recently, radio frequency identification (RFID) technology has become a key component in manufacturing, distribution industries, and banking services [1]‐[3]. Mobile RFID is widely used at the high frequency of 13.56 MHz, and in the ultra‐high frequency band from 860 to 960 MHz. The mobile RFIDs that use the 13.56 MHz carrier frequency are limited to near field communication, however this limitation is very useful in the protection of privacy and in personal authentication proc‐esses. These mobile RFIDs, using the ISO 14443 type A stan‐dard, use 100% amplitude shift keying (ASK) modulation to create a pause period. A normal clock recovery circuit has a difficulty in recovering the clock during the period. It should be noted that the ISO 14443 type A and type B meth‐ods have different modulation index values, 100% and 10%, respectively [1]. We propose a new circuit structure for an RFID trans‐ponder analog front end (AFE) which easily recovers the clock of a 100% modulated ASK signal using the ISO 14443 type A standard. A digital phase locked loop (DPLL) incorpo‐rating a charge pump enable circuit is used to recover the clock of a 100% modulated ASK signal during the pe‐riod. We also used a high voltage lateral double diffused metal‐oxide semiconductor transistor (LDMOST) [4] for the rectifier and clock recovery circuit of the DPLL at the point where the high input signal is directly applied. The proposed RFID transponder AFE was verified by circuit simulations and the measurements of a fabricated chip manufactured using the 0.18 µm complementary MOS (CMOS) standard process.

Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors

With the continuing scaling of metal–oxide–semiconductor (MOS) devices, the hot-carrier (HC)-induced device degradation has become a major reliabiliy concern in sub- and deep-submicrometre MOS field-effect transistors (MOSFETs) and lateral double-diffused MOSFETs (LDMOSFETs). It is believed that the degradation is mainly due to the effects of the generated oxide-trapped charges and interface traps at the Si/SiO2 interface. In general, the large electric field is strongly localised in a well-defined region; therefore carrier injection and interface-trap creation are similarly concentrated. The strongly inharmonious characters of HC injection and resulting damage present a considerable challenge to both experimental and modelling efforts.The HC degradation behaviour of an n-channel LDMOS transistor is investigated under various stress conditions. By applying variable base charge pumping experiments, a consistent picture of the degradation mechanism can be depicted. HC-induced interface traps are generated in the channel region of the device, in the drift region below the thick field oxide and at the bird&apos;s beak edge. The latter is shown to dominate the degradation of Idlin, which is the most critical parameter concerning HC lifetime in this specific device.

Fabricating high performance n-channel lateral double diffused metal–oxide–semiconductor transistors utilizing the shallow trench isolation as a salicide blocking mask of the drift region

In this paper, the improved characteristics of 10 V tolerant high-voltage n-channel lateral double diffused metal–oxide–semiconductor (LDMOS) devices, using a pure 0.25 μm standard low-voltage complementary metal–oxide–semiconductor (CMOS) logic process with dual gate oxide, are described. The fabricated transistors showed about 30% better current driving characteristics and about 40% higher drain operating voltage than previous reports of these kinds of devices. The transistors maintained a breakdown voltage, BV DSS , over 14 V. These devices also showed good sub-threshold characteristics. This paper describes the cost-effective and high performance n-channel high-voltage LDMOS using a pure low-voltage standard CMOS logic process.

Hot-hole-induced dielectric breakdown in LDMOS transistors

A novel failure mechanism in an n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor biased in the saturation mode is investigated. A correlation between time-to-breakdown and hot hole gate current is established and the static safe operating area (SOA), limited by hot-hole-induced dielectric breakdown, is defined. A method based on the evaluation of the time integral of an effective hot-hole gate current is proposed which allows us to estimate the time-to-fail of the device operating in any dynamic (periodic) mode, beyond its static SOA. The prebreakdown degradation of some electrical parameters, attributed to hot hole injection into the gate oxide, is also discussed.